Displaying 13 results from an estimated 13 matches for "msr_ia32_debugctlmsr".
2017 Sep 25
0
[PATCH v1 2/4] KVM/vmx: auto switch MSR_IA32_DEBUGCTLMSR
Passthrough the MSR_IA32_DEBUGCTLMSR to the guest, and take advantage of
the hardware VT-x feature to auto switch the msr upon VMExit and VMEntry.
Signed-off-by: Wei Wang <wei.w.wang at intel.com>
---
arch/x86/kvm/vmx.c | 13 ++++---------
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/arch/x86/kvm/vmx.c b/arch/...
2017 Sep 25
10
[PATCH v1 0/4] Enable LBR for the guest
...d of trapping each LBR stack MSR access, the MSRs are
passthroughed to the guest. Those MSRs are switched (i.e. load and
saved) on VMExit and VMEntry.
Test:
Try "perf record -b ./test_program" on guest.
Wei Wang (4):
KVM/vmx: re-write the msr auto switch feature
KVM/vmx: auto switch MSR_IA32_DEBUGCTLMSR
perf/x86: add a function to get the lbr stack
KVM/vmx: enable lbr for the guest
arch/x86/events/intel/lbr.c | 23 +++++++
arch/x86/include/asm/perf_event.h | 14 ++++
arch/x86/kvm/vmx.c | 135 +++++++++++++++++++++++++++++++++-----
3 files changed, 154 insertions(+), 18...
2017 Sep 25
10
[PATCH v1 0/4] Enable LBR for the guest
...d of trapping each LBR stack MSR access, the MSRs are
passthroughed to the guest. Those MSRs are switched (i.e. load and
saved) on VMExit and VMEntry.
Test:
Try "perf record -b ./test_program" on guest.
Wei Wang (4):
KVM/vmx: re-write the msr auto switch feature
KVM/vmx: auto switch MSR_IA32_DEBUGCTLMSR
perf/x86: add a function to get the lbr stack
KVM/vmx: enable lbr for the guest
arch/x86/events/intel/lbr.c | 23 +++++++
arch/x86/include/asm/perf_event.h | 14 ++++
arch/x86/kvm/vmx.c | 135 +++++++++++++++++++++++++++++++++-----
3 files changed, 154 insertions(+), 18...
2017 Sep 25
1
[PATCH v1 4/4] KVM/vmx: enable lbr for the guest
..._switch_msr(vmx, lbr_stack.lbr_info + i, 0,
> + 0);
> + }
> +}
> +
> #define VMX_XSS_EXIT_BITMAP 0
> /*
> * Sets up the vmcs for emulated real mode.
> @@ -5508,6 +5530,9 @@ static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
>
> add_atomic_switch_msr(vmx, MSR_IA32_DEBUGCTLMSR, 0, 0);
>
> + if (enable_lbrv)
> + auto_switch_lbr_msrs(vmx);
> +
> if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
> vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
>
> @@ -6721,6 +6746,28 @@ void vmx_enable_tdp(void)
> kvm_enable_tdp();
>...
2017 Sep 25
1
[PATCH v1 4/4] KVM/vmx: enable lbr for the guest
..._switch_msr(vmx, lbr_stack.lbr_info + i, 0,
> + 0);
> + }
> +}
> +
> #define VMX_XSS_EXIT_BITMAP 0
> /*
> * Sets up the vmcs for emulated real mode.
> @@ -5508,6 +5530,9 @@ static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
>
> add_atomic_switch_msr(vmx, MSR_IA32_DEBUGCTLMSR, 0, 0);
>
> + if (enable_lbrv)
> + auto_switch_lbr_msrs(vmx);
> +
> if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
> vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
>
> @@ -6721,6 +6746,28 @@ void vmx_enable_tdp(void)
> kvm_enable_tdp();
>...
2017 Sep 25
0
[PATCH v1 4/4] KVM/vmx: enable lbr for the guest
..., 0, 0);
+ if (lbr_stack.lbr_info)
+ add_atomic_switch_msr(vmx, lbr_stack.lbr_info + i, 0,
+ 0);
+ }
+}
+
#define VMX_XSS_EXIT_BITMAP 0
/*
* Sets up the vmcs for emulated real mode.
@@ -5508,6 +5530,9 @@ static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
add_atomic_switch_msr(vmx, MSR_IA32_DEBUGCTLMSR, 0, 0);
+ if (enable_lbrv)
+ auto_switch_lbr_msrs(vmx);
+
if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
@@ -6721,6 +6746,28 @@ void vmx_enable_tdp(void)
kvm_enable_tdp();
}
+static void vmx_passthrough_lbr_msrs(void)
+...
2008 Mar 14
4
[PATCH] vmx: fix debugctl handling
...==
--- 2008-03-05.orig/xen/arch/x86/hvm/vmx/vmx.c 2008-02-26 10:43:52.000000000 +0100
+++ 2008-03-05/xen/arch/x86/hvm/vmx/vmx.c 2008-03-14 14:14:40.000000000 +0100
@@ -1512,8 +1512,10 @@ static int vmx_msr_read_intercept(struct
msr_content = var_range_base[index];
break;
case MSR_IA32_DEBUGCTLMSR:
- if ( vmx_read_guest_msr(v, ecx, &msr_content) != 0 )
- msr_content = 0;
+ msr_content = __vmread(GUEST_IA32_DEBUGCTL);
+#ifdef __i386__
+ msr_content |= (u64)__vmread(GUEST_IA32_DEBUGCTL_HIGH) << 32;
+#endif
break;
case MSR_IA32_VMX_BASIC.....
2007 Apr 18
2
[PATCH] Clean up x86 control register and MSR macros (corrected)
...0269
+#define MSR_MTRRfix4K_D0000 0x0000026a
+#define MSR_MTRRfix4K_D8000 0x0000026b
+#define MSR_MTRRfix4K_E0000 0x0000026c
+#define MSR_MTRRfix4K_E8000 0x0000026d
+#define MSR_MTRRfix4K_F0000 0x0000026e
+#define MSR_MTRRfix4K_F8000 0x0000026f
+#define MSR_MTRRdefType 0x000002ff
+
+#define MSR_IA32_DEBUGCTLMSR 0x000001d9
+#define MSR_IA32_LASTBRANCHFROMIP 0x000001db
+#define MSR_IA32_LASTBRANCHTOIP 0x000001dc
+#define MSR_IA32_LASTINTFROMIP 0x000001dd
+#define MSR_IA32_LASTINTTOIP 0x000001de
+
+#define MSR_IA32_MC0_CTL 0x00000400
+#define MSR_IA32_MC0_STATUS 0x00000401
+#define MSR_IA32_MC0_ADDR 0...
2007 Apr 18
2
[PATCH] Clean up x86 control register and MSR macros (corrected)
...0269
+#define MSR_MTRRfix4K_D0000 0x0000026a
+#define MSR_MTRRfix4K_D8000 0x0000026b
+#define MSR_MTRRfix4K_E0000 0x0000026c
+#define MSR_MTRRfix4K_E8000 0x0000026d
+#define MSR_MTRRfix4K_F0000 0x0000026e
+#define MSR_MTRRfix4K_F8000 0x0000026f
+#define MSR_MTRRdefType 0x000002ff
+
+#define MSR_IA32_DEBUGCTLMSR 0x000001d9
+#define MSR_IA32_LASTBRANCHFROMIP 0x000001db
+#define MSR_IA32_LASTBRANCHTOIP 0x000001dc
+#define MSR_IA32_LASTINTFROMIP 0x000001dd
+#define MSR_IA32_LASTINTTOIP 0x000001de
+
+#define MSR_IA32_MC0_CTL 0x00000400
+#define MSR_IA32_MC0_STATUS 0x00000401
+#define MSR_IA32_MC0_ADDR 0...
2007 Apr 18
1
No subject
...0269
+#define MSR_MTRRfix4K_D0000 0x0000026a
+#define MSR_MTRRfix4K_D8000 0x0000026b
+#define MSR_MTRRfix4K_E0000 0x0000026c
+#define MSR_MTRRfix4K_E8000 0x0000026d
+#define MSR_MTRRfix4K_F0000 0x0000026e
+#define MSR_MTRRfix4K_F8000 0x0000026f
+#define MSR_MTRRdefType 0x000002ff
+
+#define MSR_IA32_DEBUGCTLMSR 0x000001d9
+#define MSR_IA32_LASTBRANCHFROMIP 0x000001db
+#define MSR_IA32_LASTBRANCHTOIP 0x000001dc
+#define MSR_IA32_LASTINTFROMIP 0x000001dd
+#define MSR_IA32_LASTINTTOIP 0x000001de
+
+#define MSR_IA32_MC0_CTL 0x00000400
+#define MSR_IA32_MC0_STATUS 0x00000401
+#define MSR_IA32_MC0_ADDR 0...
2007 Apr 18
1
No subject
...0269
+#define MSR_MTRRfix4K_D0000 0x0000026a
+#define MSR_MTRRfix4K_D8000 0x0000026b
+#define MSR_MTRRfix4K_E0000 0x0000026c
+#define MSR_MTRRfix4K_E8000 0x0000026d
+#define MSR_MTRRfix4K_F0000 0x0000026e
+#define MSR_MTRRfix4K_F8000 0x0000026f
+#define MSR_MTRRdefType 0x000002ff
+
+#define MSR_IA32_DEBUGCTLMSR 0x000001d9
+#define MSR_IA32_LASTBRANCHFROMIP 0x000001db
+#define MSR_IA32_LASTBRANCHTOIP 0x000001dc
+#define MSR_IA32_LASTINTFROMIP 0x000001dd
+#define MSR_IA32_LASTINTTOIP 0x000001de
+
+#define MSR_IA32_MC0_CTL 0x00000400
+#define MSR_IA32_MC0_STATUS 0x00000401
+#define MSR_IA32_MC0_ADDR 0...
2007 Dec 06
51
[PATCH 0/19] desc_struct integration
Hi,
this is a series of patches that unify the struct desc_struct and friends
across x86_64 and i386. As usual, it provides paravirt capabilities as a
side-effect for x86_64.
I consider the main goal, namely, of unifying the desc_struct, an ongoing
effort, being this the beginning. A lot of old code has to be touched to
accomplish that.
I don't consider this patch ready for inclusion.
2007 Dec 06
51
[PATCH 0/19] desc_struct integration
Hi,
this is a series of patches that unify the struct desc_struct and friends
across x86_64 and i386. As usual, it provides paravirt capabilities as a
side-effect for x86_64.
I consider the main goal, namely, of unifying the desc_struct, an ongoing
effort, being this the beginning. A lot of old code has to be touched to
accomplish that.
I don't consider this patch ready for inclusion.