Displaying 19 results from an estimated 19 matches for "msr_fs_base".
2013 Oct 10
10
[PATCH 0/4] x86: XSA-67 follow-up
1: correct LDT checks
2: add address validity check to guest_map_l1e()
3: use {rd,wr}{fs,gs}base when available
4: check for canonical address before doing page walks
Signed-off-by: Jan Beulich <jbeulich@suse.com>
2020 Feb 07
0
[RFC PATCH v7 18/78] KVM: vmx: pass struct kvm_vcpu to the intercept msr related functions
...R_TYPE_RW, flag);
}
}
@@ -6780,18 +6786,18 @@ static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
goto free_pml;
msr_bitmap = vmx->vmcs01.msr_bitmap;
- vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R);
- vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
- vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
- vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
- vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
- vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SY...
2020 Jul 21
0
[PATCH v9 19/84] KVM: vmx: pass struct kvm_vcpu to the intercept msr related functions
...RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
}
}
@@ -6947,18 +6953,22 @@ static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
goto free_pml;
msr_bitmap = vmx->vmcs01.msr_bitmap;
- vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R);
- vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
- vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
- vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
- vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
- vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SY...
2007 Aug 09
0
[PATCH] x86-64: pv wrmsr emulation fix
...case 0x30: /* WRMSR */
+ data = regs->eax;
+ res = ((u64)regs->edx << 32) | data;
switch ( regs->ecx )
{
#ifdef CONFIG_X86_64
@@ -1704,24 +1706,21 @@ static int emulate_privileged_op(struct
goto fail;
if ( wrmsr_safe(MSR_FS_BASE, regs->eax, regs->edx) )
goto fail;
- v->arch.guest_context.fs_base =
- ((u64)regs->edx << 32) | regs->eax;
+ v->arch.guest_context.fs_base = res;
break;
case MSR_GS_BASE:
if ( is_pv_32o...
2013 Nov 14
2
[PATCH] x86/VT-x: Disable MSR intercept for SHADOW_GS_BASE.
...changed, 1 insertion(+)
diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c
index 290b42f..4aab971 100644
--- a/xen/arch/x86/hvm/vmx/vmcs.c
+++ b/xen/arch/x86/hvm/vmx/vmcs.c
@@ -950,6 +950,7 @@ static int construct_vmcs(struct vcpu *v)
vmx_disable_intercept_for_msr(v, MSR_FS_BASE, MSR_TYPE_R | MSR_TYPE_W);
vmx_disable_intercept_for_msr(v, MSR_GS_BASE, MSR_TYPE_R | MSR_TYPE_W);
+ vmx_disable_intercept_for_msr(v, MSR_SHADOW_GS_BASE, MSR_TYPE_R | MSR_TYPE_W);
vmx_disable_intercept_for_msr(v, MSR_IA32_SYSENTER_CS, MSR_TYPE_R | MSR_TYPE_W);
vmx_...
2007 Jun 27
0
[PATCH 1/10] Provide basic Xen PM infrastructure
...SAVE_GREG(9)
+ SAVE_GREG(10)
+ SAVE_GREG(11)
+ SAVE_GREG(12)
+ SAVE_GREG(13)
+ SAVE_GREG(14)
+ SAVE_GREG(15)
+ pushfq;
+ popq SAVED_GREG(flags)
+
+ mov %cr8, GREG(ax)
+ mov GREG(ax), REF(saved_cr8)
+
+ RDMSR(MSR_FS_BASE, saved_fs_base)
+ RDMSR(MSR_GS_BASE, saved_gs_base)
+ RDMSR(MSR_SHADOW_GS_BASE, saved_kernel_gs_base)
+
+#else /* !defined(__x86_64__) */
+
+ pushfl;
+ popl SAVED_GREG(flags)
+
+#endif
+
+ mov %ds, REF(saved_ds)
+ mov %es, REF(saved_es)
+...
2007 Apr 18
1
No subject
...80 /* extended feature register */
+#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
+#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
+#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */
+#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
+#define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
+#define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
+#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
+
+/* EFER bits: */
+#define _EFER_SCE 0x00000000 /* SYSCALL/SYSRET */
+#define _EFER_LME 0x00000008 /* Long mode enable */
+#define _EFER_LMA 0x0000...
2007 Apr 18
1
No subject
...80 /* extended feature register */
+#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
+#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
+#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */
+#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
+#define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
+#define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
+#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
+
+/* EFER bits: */
+#define _EFER_SCE 0x00000000 /* SYSCALL/SYSRET */
+#define _EFER_LME 0x00000008 /* Long mode enable */
+#define _EFER_LMA 0x0000...
2020 Jul 22
0
[RFC PATCH v1 06/34] KVM: x86: mmu: add support for EPT switching
...oto free_pml;
+ if (kvm_eptp_switching_supported) {
+ err = vmx_alloc_eptp_list_page(vmx);
+ if (err)
+ goto free_pml;
+ }
+
msr_bitmap = vmx->vmcs01.msr_bitmap;
vmx_disable_intercept_for_msr(NULL, msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R);
vmx_disable_intercept_for_msr(NULL, msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h
index 14f0b9102d58..4e2f86458ca2 100644
--- a/arch/x86/kvm/vmx/vmx.h
+++ b/arch/x86/kvm/vmx/vmx.h
@@ -297,6 +297,7 @@ struct vcpu_vmx {
struct pt_desc pt_desc;
+ struct page *eptp_list_pg;
/* The view this vcpu oper...
2007 Apr 18
2
[PATCH] Clean up x86 control register and MSR macros (corrected)
...80 /* extended feature register */
+#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
+#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
+#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */
+#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
+#define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
+#define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
+#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
+
+/* EFER bits: */
+#define _EFER_SCE 0x00000000 /* SYSCALL/SYSRET */
+#define _EFER_LME 0x00000008 /* Long mode enable */
+#define _EFER_LMA 0x0000...
2007 Apr 18
2
[PATCH] Clean up x86 control register and MSR macros (corrected)
...80 /* extended feature register */
+#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
+#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
+#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */
+#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
+#define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
+#define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
+#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
+
+/* EFER bits: */
+#define _EFER_SCE 0x00000000 /* SYSCALL/SYSRET */
+#define _EFER_LME 0x00000008 /* Long mode enable */
+#define _EFER_LMA 0x0000...
2019 Aug 09
0
[RFC PATCH v6 55/92] kvm: introspection: add KVMI_CONTROL_MSR and KVMI_EVENT_MSR
...2cd146ccc6ff..ac027471c4f3 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -1319,6 +1319,9 @@ EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
*/
int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
{
+ if (!kvmi_msr_event(vcpu, msr))
+ return 1;
+
switch (msr->index) {
case MSR_FS_BASE:
case MSR_GS_BASE:
@@ -10083,6 +10086,13 @@ bool kvm_vector_hashing_enabled(void)
}
EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
+void kvm_arch_msr_intercept(struct kvm_vcpu *vcpu, unsigned int msr,
+ bool enable)
+{
+ kvm_x86_ops->msr_intercept(vcpu, msr, enable);
+}
+EXPORT_SYMBOL_G...
2007 Apr 18
1
[RFC/PATCH LGUEST X86_64 03/13] lguest64 core
...t;< 32)-1)) |
+ (vcpu->guest_gs_shadow_d << 32);
+ lhwrite_u64(vcpu, regs->rbx, val);
+ break;
+ case MSR_GS_BASE:
+ val = (vcpu->guest_gs_a & ((1UL << 32)-1)) |
+ (vcpu->guest_gs_d << 32);
+ lhwrite_u64(vcpu, regs->rbx, val);
+ break;
+ case MSR_FS_BASE:
+ lhwrite_u64(vcpu, regs->rbx, 0);
+ break;
+ case MSR_EFER:
+ val = EFER_SCE | EFER_LME | EFER_LMA | EFER_NX;
+ lhwrite_u64(vcpu, regs->rbx, val);
+ break;
+ default:
+ kill_guest_dump(vcpu, "bad read of msr %llx\n", regs->rdx);
+ }
+ break;
+ case LHCALL_WRMSR:
+...
2007 Apr 18
1
[RFC/PATCH LGUEST X86_64 03/13] lguest64 core
...t;< 32)-1)) |
+ (vcpu->guest_gs_shadow_d << 32);
+ lhwrite_u64(vcpu, regs->rbx, val);
+ break;
+ case MSR_GS_BASE:
+ val = (vcpu->guest_gs_a & ((1UL << 32)-1)) |
+ (vcpu->guest_gs_d << 32);
+ lhwrite_u64(vcpu, regs->rbx, val);
+ break;
+ case MSR_FS_BASE:
+ lhwrite_u64(vcpu, regs->rbx, 0);
+ break;
+ case MSR_EFER:
+ val = EFER_SCE | EFER_LME | EFER_LMA | EFER_NX;
+ lhwrite_u64(vcpu, regs->rbx, val);
+ break;
+ default:
+ kill_guest_dump(vcpu, "bad read of msr %llx\n", regs->rdx);
+ }
+ break;
+ case LHCALL_WRMSR:
+...
2020 Jul 22
34
[RFC PATCH v1 00/34] VM introspection - EPT Views and Virtualization Exceptions
This patch series is based on the VM introspection patches
(https://lore.kernel.org/kvm/20200721210922.7646-1-alazar at bitdefender.com/),
extending the introspection API with EPT Views and Virtualization
Exceptions (#VE) support.
The purpose of this series is to get an initial feedback and to see if
we are on the right track, especially because the changes made to add
the EPT views are not small
2019 Aug 09
117
[RFC PATCH v6 00/92] VM introspection
The KVM introspection subsystem provides a facility for applications running
on the host or in a separate VM, to control the execution of other VM-s
(pause, resume, shutdown), query the state of the vCPUs (GPRs, MSRs etc.),
alter the page access bits in the shadow page tables (only for the hardware
backed ones, eg. Intel's EPT) and receive notifications when events of
interest have taken place
2019 Aug 09
117
[RFC PATCH v6 00/92] VM introspection
The KVM introspection subsystem provides a facility for applications running
on the host or in a separate VM, to control the execution of other VM-s
(pause, resume, shutdown), query the state of the vCPUs (GPRs, MSRs etc.),
alter the page access bits in the shadow page tables (only for the hardware
backed ones, eg. Intel's EPT) and receive notifications when events of
interest have taken place
2020 Feb 07
78
[RFC PATCH v7 00/78] VM introspection
The KVM introspection subsystem provides a facility for applications
running on the host or in a separate VM, to control the execution of
other VMs (pause, resume, shutdown), query the state of the vCPUs (GPRs,
MSRs etc.), alter the page access bits in the shadow page tables (only
for the hardware backed ones, eg. Intel's EPT) and receive notifications
when events of interest have taken place
2020 Jul 21
87
[PATCH v9 00/84] VM introspection
The KVM introspection subsystem provides a facility for applications
running on the host or in a separate VM, to control the execution of
other VMs (pause, resume, shutdown), query the state of the vCPUs (GPRs,
MSRs etc.), alter the page access bits in the shadow page tables (only
for the hardware backed ones, eg. Intel's EPT) and receive notifications
when events of interest have taken place