Displaying 1 result from an estimated 1 matches for "msr_f10_mc4_misc3".
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msr_f10_mc4_misc2
2013 Jan 17
0
[PATCH v2] AMD: Enable WC+ memory type on family 10 processors
...set them manually.
*/
diff -r b6195e277da5 -r 40881d58e991 xen/include/asm-x86/msr-index.h
--- a/xen/include/asm-x86/msr-index.h Wed Jan 16 14:15:44 2013 +0000
+++ b/xen/include/asm-x86/msr-index.h Thu Jan 17 14:47:04 2013 -0500
@@ -220,8 +220,9 @@
#define MSR_F10_MC4_MISC2 0xc0000409
#define MSR_F10_MC4_MISC3 0xc000040A
-/* AMD Family10h MMU control MSRs */
-#define MSR_F10_BU_CFG 0xc0011023
+/* AMD Family10h Bus Unit MSRs */
+#define MSR_F10_BU_CFG 0xc0011023
+#define MSR_F10_BU_CFG2 0xc001102a
/* Other AMD Fam10h MSRs */
#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058