search for: msixtbl_entri

Accelerated msix entry is initialized to zero when msixtbl_pt_register is called. This doesn''t match the value from qemu side, although pirq may already be mapped and binded in qemu side. Kernel will get wrong value when reading msix info. Signed-off-by: Zhenzhong Duan <zhenzhong.duan@oracle.com> Tested-by: Yuval Shaia <yuval.shaia@oracle.com> --- tools/libxc/xc_domain.c

Guest needs the ability to enable and disable MSI-X interrupts by setting the MSI-X control bit, for a passed-through device. Guest is allowed to write MSI-X mask bit only if Xen *thinks* that mask is clear (interrupts enabled). If the mask is set by Xen (interrupts disabled), writes to mask bit by the guest is ignored. Currently, a write to MSI-X mask bit by the guest is silently ignored. A

Guest needs the ability to enable and disable MSI-X interrupts by setting the MSI-X control bit, for a passed-through device. Guest is allowed to write MSI-X mask bit only if Xen *thinks* that mask is clear (interrupts enabled). If the mask is set by Xen (interrupts disabled), writes to mask bit by the guest is ignored. Currently, a write to MSI-X mask bit by the guest is silently ignored. A

flight 12413 xen-4.0-testing real [real] http://www.chiark.greenend.org.uk/~xensrcts/logs/12413/ Regressions :-( Tests which did not succeed and are blocking, including tests which could not be run: build-amd64 4 xen-build fail REGR. vs. 12202 build-amd64-pvops 4 kernel-build fail REGR. vs. 12202 build-amd64-oldkern 4