search for: msi_attrib

PCI devices save the msi and msix capability offset in pci_dev->msi_cap and pci_dev->msix_cap. When we access PCI device MSI and MSIX registers, we can use msi_cap and msix_cap in pci_dev directly. Remove the pos member in msi_attrib. Signed-off-by: Yijing Wang <wangyijing at huawei.com> --- arch/mips/pci/msi-octeon.c | 4 ++-- drivers/pci/host/pcie-designware.c | 2 +- drivers/pci/msi.c | 2 -- include/linux/msi.h | 1 - 4 files changed, 3 insertions(+), 6 deletions(-...

...__setup_irq-> irq_startup-> __startup_pirq-> EVTCHNOP_bind_pirq hypercall (trap into Xen) [Xen:] pirq_guest_bind-> startup_msi_irq-> unmask_msi_irq-> msi_set_mask_bit-> entry->msi_attrib.masked = 0 So entry->msi_attrib.masked in xen side always has newest value. entry->masked in initial domain is untouched and is 1 after msix_capability_init. Based on above, it''s Xen''s duty to restore entry->msi_attrib.masked to device, but with current code, entry->...

...; +{ > + struct msi_desc *entry; > + > + list_for_each_entry(entry, &msi->msi_list, list) { > + int i, nvec; > + if (entry->irq == 0) > + continue; > + if (entry->nvec_used) > + nvec = entry->nvec_used; > + else > + nvec = 1 << entry->msi_attrib.multiple; > + for (i = 0; i < nvec; i++) > + arch_teardown_msi_irq(entry->irq + i); > + } > +} > + > +static void default_restore_msi_irq(struct msi_irqs *msi, int irq) > +{ > + struct msi_desc *entry; > + > + entry = NULL; > + if (msi->msix_enabled) { &...

...; +{ > + struct msi_desc *entry; > + > + list_for_each_entry(entry, &msi->msi_list, list) { > + int i, nvec; > + if (entry->irq == 0) > + continue; > + if (entry->nvec_used) > + nvec = entry->nvec_used; > + else > + nvec = 1 << entry->msi_attrib.multiple; > + for (i = 0; i < nvec; i++) > + arch_teardown_msi_irq(entry->irq + i); > + } > +} > + > +static void default_restore_msi_irq(struct msi_irqs *msi, int irq) > +{ > + struct msi_desc *entry; > + > + entry = NULL; > + if (msi->msix_enabled) { &...

...oid default_teardown_msi_irqs(struct msi_irqs *msi) +{ + struct msi_desc *entry; + + list_for_each_entry(entry, &msi->msi_list, list) { + int i, nvec; + if (entry->irq == 0) + continue; + if (entry->nvec_used) + nvec = entry->nvec_used; + else + nvec = 1 << entry->msi_attrib.multiple; + for (i = 0; i < nvec; i++) + arch_teardown_msi_irq(entry->irq + i); + } +} + +static void default_restore_msi_irq(struct msi_irqs *msi, int irq) +{ + struct msi_desc *entry; + + entry = NULL; + if (msi->msix_enabled) { + list_for_each_entry(entry, &msi->msi_list, lis...

...} int msi_free_irq(struct msi_desc *entry) @@ -1018,19 +1058,20 @@ static void dump_msi(unsigned char key) { struct irq_desc *desc = irq_to_desc(irq); const struct msi_desc *entry; - u32 addr, data; + u32 addr, data, dest32; + int mask; + struct msi_attrib attr; unsigned long flags; char type; spin_lock_irqsave(&desc->lock, flags); entry = desc->msi_desc; - type = desc->handler == &pci_msi_type && entry; - - spin_unlock_irqrestore(&desc->lock, flags); - - if...

...ct msi_desc and alloc the irq, then write the msi address/data value to hardware registers. This series only did compile test, we will test it in x86 and arm platform later. Any comments are welcome. Thanks! Yijing. Yijing Wang (11): PCI/MSI: Use pci_dev->msi_cap instead of msi_desc->msi_attrib.pos PCI/MSI: Use new MSI type macro instead of PCI MSI flags PCI/MSI: Refactor pci_dev_msi_enabled() PCI/MSI: Move MSIX table address mapping out of msix_capability_init PCI/MSI: Move populate_msi_sysfs() out of msi_capability_init() PCI/MSI: Save MSI irq in PCI MSI layer PCI/MSI: Mask...

...ct msi_desc and alloc the irq, then write the msi address/data value to hardware registers. This series only did compile test, we will test it in x86 and arm platform later. Any comments are welcome. Thanks! Yijing. Yijing Wang (11): PCI/MSI: Use pci_dev->msi_cap instead of msi_desc->msi_attrib.pos PCI/MSI: Use new MSI type macro instead of PCI MSI flags PCI/MSI: Refactor pci_dev_msi_enabled() PCI/MSI: Move MSIX table address mapping out of msix_capability_init PCI/MSI: Move populate_msi_sysfs() out of msi_capability_init() PCI/MSI: Save MSI irq in PCI MSI layer PCI/MSI: Mask...

...* Don't shift by >= width of type */ @@ -175,6 +185,7 @@ static inline __attribute_const__ u32 msi_mask(unsigned x) */ u32 default_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) { + struct pci_dev *dev = desc->msi->data; u32 mask_bits = desc->masked; if (!desc->msi_attrib.maskbit) @@ -182,7 +193,7 @@ u32 default_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) mask_bits &= ~mask; mask_bits |= flag; - pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits); + pci_write_config_dword(dev, desc->mask_pos, mask_bits); return mask_bits;...

...86/hvm/vmsi.c @@ -187,6 +187,19 @@ static struct msixtbl_entry *msixtbl_find_entry( return NULL; } +static struct msi_desc *virt_to_msi_desc(struct pci_dev *dev, void *virt) +{ + struct msi_desc *desc; + + list_for_each_entry( desc, &dev->msi_list, list ) + if ( desc->msi_attrib.type == PCI_CAP_ID_MSIX && + desc->mask_base + PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET + == virt ) + return desc; + + return NULL; +} + static void __iomem *msixtbl_addr_to_virt( struct msixtbl_entry *entry, unsigned long addr) { @@ -247,13 +26...

...gt; current power state is not D0, because checking code in __write_msi_msi. > > void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) > { > if (entry->dev->current_state != PCI_D0) { > /* Don't touch the hardware now */ > } else if (entry->msi_attrib.is_msix) { > void __iomem *base; > base = entry->mask_base + > entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; > > writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); > writel(msg->address_hi, base + PCI_MSIX_ENTRY_U...

...e */ > @@ -175,6 +185,7 @@ static inline __attribute_const__ u32 msi_mask(unsigned x) > */ > u32 default_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) > { > + struct pci_dev *dev = desc->msi->data; > u32 mask_bits = desc->masked; > > if (!desc->msi_attrib.maskbit) > @@ -182,7 +193,7 @@ u32 default_msi_mask_irq(struct msi_desc *desc, u32 mask, > u32 flag) > > mask_bits &= ~mask; > mask_bits |= flag; > - pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits); > + pci_write_config_dword(dev, desc->mask_pos,...

...e */ > @@ -175,6 +185,7 @@ static inline __attribute_const__ u32 msi_mask(unsigned x) > */ > u32 default_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) > { > + struct pci_dev *dev = desc->msi->data; > u32 mask_bits = desc->masked; > > if (!desc->msi_attrib.maskbit) > @@ -182,7 +193,7 @@ u32 default_msi_mask_irq(struct msi_desc *desc, u32 mask, > u32 flag) > > mask_bits &= ~mask; > mask_bits |= flag; > - pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits); > + pci_write_config_dword(dev, desc->mask_pos,...

...is not D0, because checking code in __write_msi_msi. >> >> void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) >> { >> if (entry->dev->current_state != PCI_D0) { >> /* Don't touch the hardware now */ >> } else if (entry->msi_attrib.is_msix) { >> void __iomem *base; >> base = entry->mask_base + >> entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; >> >> writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); >> writel(msg->address_hi,...

...ngular(&dev->msi_list)); > - msidesc = list_entry(dev->msi_list.next, struct msi_desc, list); > + WARN_ON(!list_is_singular(&msi->msi_list)); > + msidesc = list_entry(msi->msi_list.next, struct msi_desc, list); > WARN_ON(msidesc->irq); > WARN_ON(msidesc->msi_attrib.multiple); > WARN_ON(msidesc->nvec_used); > > - irq = irq_alloc_hwirqs(nvec, dev_to_node(&dev->dev)); > + irq = irq_alloc_hwirqs(nvec, msi->node); > if (irq == 0) > return -ENOSPC; > > @@ -70,18 +70,18 @@ static int do_setup_msi_irqs(struct pci_dev *dev...

...ngular(&dev->msi_list)); > - msidesc = list_entry(dev->msi_list.next, struct msi_desc, list); > + WARN_ON(!list_is_singular(&msi->msi_list)); > + msidesc = list_entry(msi->msi_list.next, struct msi_desc, list); > WARN_ON(msidesc->irq); > WARN_ON(msidesc->msi_attrib.multiple); > WARN_ON(msidesc->nvec_used); > > - irq = irq_alloc_hwirqs(nvec, dev_to_node(&dev->dev)); > + irq = irq_alloc_hwirqs(nvec, msi->node); > if (irq == 0) > return -ENOSPC; > > @@ -70,18 +70,18 @@ static int do_setup_msi_irqs(struct pci_dev *dev...

...ing code in __write_msi_msi. >>> >>> void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) >>> { >>> if (entry->dev->current_state != PCI_D0) { >>> /* Don't touch the hardware now */ >>> } else if (entry->msi_attrib.is_msix) { >>> void __iomem *base; >>> base = entry->mask_base + >>> entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; >>> >>> writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); >>> wr...

...; - WARN_ON(!list_is_singular(&dev->msi_list)); - msidesc = list_entry(dev->msi_list.next, struct msi_desc, list); + WARN_ON(!list_is_singular(&msi->msi_list)); + msidesc = list_entry(msi->msi_list.next, struct msi_desc, list); WARN_ON(msidesc->irq); WARN_ON(msidesc->msi_attrib.multiple); WARN_ON(msidesc->nvec_used); - irq = irq_alloc_hwirqs(nvec, dev_to_node(&dev->dev)); + irq = irq_alloc_hwirqs(nvec, msi->node); if (irq == 0) return -ENOSPC; @@ -70,18 +70,18 @@ static int do_setup_msi_irqs(struct pci_dev *dev, int nvec) msidesc->msi_attrib.m...

On Thu, Jul 3, 2014 at 10:35 PM, Yijing Wang <wangyijing at huawei.com> wrote: > Hi Brian, > From your 01:00.0 VGA compatible controller PCI config register, it supports 1 MSI vector, so I think this > card has no problem. But you didn't answer what's the pci_enable_msi() return during it enable MSI fail. > > You can check PCI bus whether support MSI like: > >

...s success, so I guess the device current power state is not D0, because checking code in __write_msi_msi. void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) { if (entry->dev->current_state != PCI_D0) { /* Don't touch the hardware now */ } else if (entry->msi_attrib.is_msix) { void __iomem *base; base = entry->mask_base + entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); writel(ms...