search for: msa128d

Displaying 9 results from an estimated 9 matches for "msa128d".

2017 Feb 21
2
Error at Pre-regalloc Machine LICM: "getVRegDef assumes a single definition or no definition"' failed.
...BUILD_VECTOR, which gets converted in my back end's machine instrution VLOAD_D, although the custom code seems to always select instructions in a valid way.) ******** Pre-regalloc Machine LICM: Test ******** Entering BB#4 Hoist non-reg-pressure: %vreg50<def> = VLOAD_D 1; MSA128D:%vreg50 dbg:IfVectorize.c:37:16 Hoisting %vreg50<def> = VLOAD_D 1; MSA128D:%vreg50 dbg:IfVectorize.c:37:16 from BB#4 to BB#3 Hoist non-reg-pressure: %vreg51<def> = VLOAD_D 0; MSA128D:%vreg51 Hoisting %vreg51<def> = VLOAD_D 0; MSA128D:%vreg51 from BB#4 to...
2016 Oct 24
2
Instruction selection confusion at register - chooses vector register instead of scalar one
Hello. I have extended the BPF back end with vector registers (inspiring from Mips MSA) - something like this: def MSA128D: RegisterClass<"Connex", [v128i16], 32, (sequence "Wh%u", 0, 31)>; I also added vector store and load instructions in the style of Mips MSA - see https://github.com/llvm-mirror/llvm/blob/master/lib/Target/Mips/MipsMSAInstrInfo.td, look fo...
2016 Oct 25
0
Instruction selection confusion at register - chooses vector register instead of scalar one
...-Matt On Tue, Oct 25, 2016 at 7:30 AM +0800, "Alex Susu via llvm-dev" <llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org>> wrote: Hello. I have extended the BPF back end with vector registers (inspiring from Mips MSA) - something like this: def MSA128D: RegisterClass<"Connex", [v128i16], 32, (sequence "Wh%u", 0, 31)>; I also added vector store and load instructions in the style of Mips MSA - see https://github.com/llvm-mirror/llvm/blob/master/lib/Target/Mips/MipsMSAInstrInfo.td, look for...
2016 Jun 28
2
Instruction selection problem with type i64 - mistaken as v8i64?
...: LOAD<SizeOp, OpcodeStr, [(set i64:$dst, (OpNode ADDRri:$addr))]>; So I am surprised that the instruction selector finds as match for operand i64:$dst the vector register REGVEC0, which has type v8i64 as defined below, inspired from lib/Target/Mips/MipsRegisterInfo.td: def MSA128D: RegisterClass<"Connex", [v8i64], 512, (sequence "Wd%u", 0, 31)>; Can anybody help with an idea what I can do to fix this problem? Below are a few possibly useful lines from the output of llc, related to the instr. selection and reg...
2016 Oct 29
1
Problems with Inline ASM expressions generated in the back end
...ion) I get this error at compilation (at scheduling): BB#0: derived from LLVM BB %entry Live Ins: %R1 %R2 %vreg6<def> = COPY %R2; GPR:%vreg6 %vreg5<def> = COPY %R1; GPR:%vreg5 %vreg12<def> = VLOAD_D_WO_IMM; MSA128D:%vreg12 dbg:IfVectorize.c:39:5 INLINEASM <es: (Param1 - Param2); // MSA_I10> [sideeffect] [attdialect], <llc: /llvm/include/llvm/Support/Casting.h:237: typename llvm::cast_retty<X, Y*>::ret_type llvm::cast(Y*) [with X = llvm::ValueAsMetadata; Y = const llvm::Me...
2016 Jun 29
0
Instruction selection problem with type i64 - mistaken as v8i64?
...[(set i64:$dst, (OpNode ADDRri:$addr))]>; > > So I am surprised that the instruction selector finds as match for operand > i64:$dst > the vector register REGVEC0, which has type v8i64 as defined below, inspired > from > lib/Target/Mips/MipsRegisterInfo.td: > def MSA128D: RegisterClass<"Connex", [v8i64], 512, > (sequence "Wd%u", 0, 31)>; > > Can anybody help with an idea what I can do to fix this problem? > > Below are a few possibly useful lines from the output of llc, related to the...
2016 Dec 15
2
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
...} > // Gather mem operands > class X86VMemOperand<RegisterClass RC, string printMethod> > : X86MemOperand<printMethod> { > let MIOperandInfo = (ops i8imm, RC, i32imm); > } > def vx256xmem : X86VMemOperand<MSA128D, "printi256mem">; > > def vectoraddr : ComplexPattern<iPTR, 5, "selectVectorAddr", [],[SDNPWantParent]>; > > class LD_INDIRECT_DESC_BASE2<string instr_asm, > RegisterOperand ROWD, >...
2016 Dec 12
0
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
...;OPERAND_MEMORY"; } // Gather mem operands class X86VMemOperand<RegisterClass RC, string printMethod> : X86MemOperand<printMethod> { let MIOperandInfo = (ops i8imm, RC, i32imm); } def vx256xmem : X86VMemOperand<MSA128D, "printi256mem">; def vectoraddr : ComplexPattern<iPTR, 5, "selectVectorAddr", [],[SDNPWantParent]>; class LD_INDIRECT_DESC_BASE2<string instr_asm, RegisterOperand ROWD, Reg...
2016 Dec 11
2
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
...attern = [(set ROWD:$wd, (TyNode (masked_gather ROWSP:$wsp, VK128Opnd :$wsm, ROWSI:$wsptr, ROWSI:$wsi)))]; InstrItinClass Itinerary = itin; string DecoderMethod = "DecodeMSA128Mem"; } class LD_INDIRECT_D_DESC2 : LD_INDIRECT_DESC_BASE2<"read", v128i16, MSA128DOpnd>; class LD_INDIRECT_D_ENC2 : MSA_2R_FMT<0b101001110>; def LD_INDIRECT_D2: LD_INDIRECT_D_ENC2, LD_INDIRECT_D_DESC2; /* // From http://llvm.org/docs/doxygen/html/SelectionDAGNodes_8h_source.html: 02115 // In the both nodes address is Op1, mask is Op2:...