Displaying 20 results from an estimated 37 matches for "mrmdestmem".
2015 Mar 24
3
[LLVMdev] [PATCH] fix outs/ins of MOV16mr instruction (X86)
...MOV16mr instruction of X86.
Thanks.
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index e9a0431..f5b2064 100644
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -1412,7 +1412,7 @@ let SchedRW = [WriteStore] in {
def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
"mov{b}\t{$src, $dst|$dst, $src}",
[(store GR8:$src, addr:$dst)], IIC_MOV_MEM>;
-def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
+def MOV16mr : I<0x89, MRMDestMem, (outs i16mem:$dst),...
2017 Jul 11
2
error: In anonymous_4820: Unrecognized node 'VRR128'!
hello,
i need to use v32i32 and v32f32 in store instructions.
I defined my register as;
def VRR128 : RegisterClass<"X86", [v32i32, v32f32],
1024, (add R_0_V_0, R_1_V_0, R_2_V_0)>;
def STORE_DWORD : I<0x70, MRMDestMem, (outs), (ins i2048mem:$dst,
VRR128:$src),
"STORE_DWORD\t{$src, $dst|$dst, $src}",
[(store (v32i32 (bitconvert VRR128:$src)), addr:$dst)],
IIC_MOV_MEM>, TA;
def: Pat<(store (v32f32 (bitconvert (VRR128:$src))), addr:$dst),
(STORE_DWORD addr:...
2017 Jul 07
2
Unhandled reg/opcode register encoding VR2048 Error in backend
...M : I<0x6F, MRMSrcMem, (outs VR2048:$dst), (ins
i32mem:$src),
"vmov_256B_rm\t{$src, $dst|$dst, $src}",
[(set VR2048:$dst, (v64i32 (scalar_to_vector (loadi32
addr:$src))))],
IIC_MOV_MEM>, EVEX;
def VMOV_256B_MR : I<0x7F, MRMDestMem, (outs), (ins i32mem:$dst,
VR2048:$src),
"vmov_256B_mr\t{$src, $dst|$dst, $src}",
[(store (i32 (bitconvert VR2048:$src)), addr:$dst)],
IIC_MOV_MEM>, EVEX;
here i have already define VR2048 in x86registerinfo.td as;
def R256B_0: X86Reg<"...
2017 Jul 11
2
error: In anonymous_4820: Unrecognized node 'VRR128'!
...; i need to use v32i32 and v32f32 in store instructions.
>> I defined my register as;
>>
>> def VRR128 : RegisterClass<"X86", [v32i32, v32f32],
>> 1024, (add R_0_V_0, R_1_V_0, R_2_V_0)>;
>>
>> def STORE_DWORD : I<0x70, MRMDestMem, (outs), (ins i2048mem:$dst,
>> VRR128:$src),
>> "STORE_DWORD\t{$src, $dst|$dst, $src}",
>> [(store (v32i32 (bitconvert VRR128:$src)),
>> addr:$dst)], IIC_MOV_MEM>, TA;
>>
>>
>>
>> def: Pat<(stor...
2017 Jul 11
2
error: In anonymous_4820: Unrecognized node 'VRR128'!
...uctions.
>>>> I defined my register as;
>>>>
>>>> def VRR128 : RegisterClass<"X86", [v32i32, v32f32],
>>>> 1024, (add R_0_V_0, R_1_V_0, R_2_V_0)>;
>>>>
>>>> def STORE_DWORD : I<0x70, MRMDestMem, (outs), (ins i2048mem:$dst,
>>>> VRR128:$src),
>>>> "STORE_DWORD\t{$src, $dst|$dst, $src}",
>>>> [(store (v32i32 (bitconvert VRR128:$src)),
>>>> addr:$dst)], IIC_MOV_MEM>, TA;
>>>>
>...
2004 Dec 02
3
[LLVMdev] Adding xadd instruction to X86
...9;m trying to add the xadd instruction to the X86 back end.
xadd r/m32, r32
exchanges r/m32 and r32, and loads the sum into r/m32. I'm
interested in the case where the destination operand is a
memory location.
I've added the following entry to X86InstrInfo.td:
def XADD32mr : I<0x87, MRMDestMem,
(ops i32mem:$src1, R32:$src2),
"xadd{l} {$src1|$src2}, {$src2|$src1}">;
The xadd is emitted for the intrinsic function:
call int (<integer type>*, <integer type>)*
%llvm.atomic_fetch_add_store(<integer type>* <pointer>,...
2010 Feb 15
4
[LLVMdev] Botched Build
On Feb 15, 2010, at 1:04 PM, David Greene wrote:
>> FWIW, this is because you broke the encoding of an instruction in your
>> patch. This is incorrect:
>>
>> +def MOVNTDQ_64mr : PSI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst,
>> VR128:$src), + "movntdq\t{$src, $dst|$dst, $src}",
>> + [(alignednontemporalstore (v2f64 VR128:$src),
>> addr:$dst)]>;
>>
>> Please don't check in patches when you know that they bre...
2010 Feb 15
2
[LLVMdev] Botched Build
...coding.s has been failing
>> for a while, maybe someone should mark it XFAIL?
>
> It passed for me until you applied your patch, I reverted it in r96265.
FWIW, this is because you broke the encoding of an instruction in your patch. This is incorrect:
+def MOVNTDQ_64mr : PSI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
+ "movntdq\t{$src, $dst|$dst, $src}",
+ [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
Please don't check in patches when you know that they break testcases.
-Chris
2007 Dec 12
2
[LLVMdev] Bogus X86-64 Patterns
...oPQIrm : RPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
"mov{d|q}\t{$src, $dst|$dst, $src}",
[(set VR128:$dst,
(v2i64 (scalar_to_vector (loadi64 addr:$src))))]>;
def MOVPQIto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, VR128:
$src),
"mov{d|q}\t{$src, $dst|$dst, $src}",
[(store (i64 (vector_extract (v2i64 VR128:$src),
(iPTR 0))), addr:$dst)]>;
These say that for an AT&T-style assemb...
2010 Feb 15
3
[LLVMdev] Botched Build
...bruary 2010 15:08:22 Chris Lattner wrote:
>> On Feb 15, 2010, at 1:04 PM, David Greene wrote:
>>>> FWIW, this is because you broke the encoding of an instruction in your
>>>> patch. This is incorrect:
>>>>
>>>> +def MOVNTDQ_64mr : PSI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst,
>>>> VR128:$src), + "movntdq\t{$src, $dst|$dst, $src}",
>>>> + [(alignednontemporalstore (v2f64 VR128:$src),
>>>> addr:$dst)]>;
>>>>
>>>> Please don't chec...
2010 Feb 15
0
[LLVMdev] Botched Build
On Monday 15 February 2010 15:08:22 Chris Lattner wrote:
> On Feb 15, 2010, at 1:04 PM, David Greene wrote:
> >> FWIW, this is because you broke the encoding of an instruction in your
> >> patch. This is incorrect:
> >>
> >> +def MOVNTDQ_64mr : PSI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst,
> >> VR128:$src), + "movntdq\t{$src, $dst|$dst, $src}",
> >> + [(alignednontemporalstore (v2f64 VR128:$src),
> >> addr:$dst)]>;
> >>
> >> Please don't check in patches whe...
2007 Aug 01
2
[LLVMdev] Adding custom operation intrinsic for ASIP architectures.
...ith "llvm.x86.".
> def int_x86_sse_movnt_ps : GCCBuiltin<"__builtin_ia32_movntps">,
> Intrinsic<[llvm_void_ty, llvm_ptr_ty,
> llvm_v4f32_ty], [IntrWriteMem]>;
> }
>
> and lib/Target/X86/X86InstrSSE.td contains:
>
> def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst,
> VR128:$src),
> "movntps {$src, $dst|$dst, $src}",
> [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
>
> There is corresponding code in llvm-gcc to tell GCC how to handle this
> builtin. Is this what you're looking for?
>
Yes thi...
2010 Feb 15
0
[LLVMdev] Botched Build
...t; for a while, maybe someone should mark it XFAIL?
> >
> > It passed for me until you applied your patch, I reverted it in r96265.
>
> FWIW, this is because you broke the encoding of an instruction in your
> patch. This is incorrect:
>
> +def MOVNTDQ_64mr : PSI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst,
> VR128:$src), + "movntdq\t{$src, $dst|$dst, $src}",
> + [(alignednontemporalstore (v2f64 VR128:$src),
> addr:$dst)]>;
>
> Please don't check in patches when you know that they break testcases.
I cert...
2007 Aug 02
0
[LLVMdev] Adding custom operation intrinsic for ASIP architectures.
On Wed, 1 Aug 2007, [UTF-8] Mikael Lepist? wrote:
>> def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst,
>> VR128:$src),
>> "movntps {$src, $dst|$dst, $src}",
>> [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
>>
>> There is corresponding code in llvm-gcc to tell GCC how to handle this
>> builtin. Is this what you're l...
2015 Mar 25
3
[LLVMdev] [PATCH] fix outs/ins of MOV16mr instruction (X86)
.../Target/X86/X86InstrInfo.td
> b/lib/Target/X86/X86InstrInfo.td
> > index e9a0431..f5b2064 100644
> > --- a/lib/Target/X86/X86InstrInfo.td
> > +++ b/lib/Target/X86/X86InstrInfo.td
> > @@ -1412,7 +1412,7 @@ let SchedRW = [WriteStore] in {
> > def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
> > "mov{b}\t{$src, $dst|$dst, $src}",
> > [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>;
> > -def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
> > +def MOV16mr : I&...
2004 Dec 02
0
[LLVMdev] Adding xadd instruction to X86
...uction to the X86 back end.
> xadd r/m32, r32
> exchanges r/m32 and r32, and loads the sum into r/m32. I'm
> interested in the case where the destination operand is a
> memory location.
>
> I've added the following entry to X86InstrInfo.td:
> def XADD32mr : I<0x87, MRMDestMem,
> (ops i32mem:$src1, R32:$src2),
This looks fine.
> "xadd{l} {$src1|$src2}, {$src2|$src1}">;
I haven't checked this, but it's probably fine.
> The xadd is emitted for the intrinsic function:
> call int (<integer type>*, <...
2007 Aug 01
0
[LLVMdev] Adding custom operation intrinsic for ASIP architectures.
...uot;llvm.x86.".
def int_x86_sse_movnt_ps : GCCBuiltin<"__builtin_ia32_movntps">,
Intrinsic<[llvm_void_ty, llvm_ptr_ty,
llvm_v4f32_ty], [IntrWriteMem]>;
}
and lib/Target/X86/X86InstrSSE.td contains:
def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
"movntps {$src, $dst|$dst, $src}",
[(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
There is corresponding code in llvm-gcc to tell GCC how to handle this
builtin. Is this what you're looking for?...
2009 Dec 02
5
[LLVMdev] Selecting Vector Shuffle of Different Types
The AVX saga continues.
I am attempting to write a pattern for VEXTRACTF128 but am having some
problems. My attempt looks something like this:
defm EXTRACTF128 : avx_fp_extract_vector_osta_node_mri_256<0x19, MRMDestReg,
MRMDestMem, "extractf128", undef, X86f32, X86i32i8,
// rr
[(set VR128:$dst,
(v4f32 (vector_shuffle
(v8f32 undef), (v8f32 VR256:$src1),
VEXTRACTF128_shuffle_mask:$...
2004 Dec 03
2
[LLVMdev] Adding xadd instruction to X86
...end.
>>xadd r/m32, r32
>>exchanges r/m32 and r32, and loads the sum into r/m32. I'm
>>interested in the case where the destination operand is a
>>memory location.
>>
>>I've added the following entry to X86InstrInfo.td:
>>def XADD32mr : I<0x87, MRMDestMem,
>> (ops i32mem:$src1, R32:$src2),
>
>
> This looks fine.
>
>
>> "xadd{l} {$src1|$src2}, {$src2|$src1}">;
>
>
> I haven't checked this, but it's probably fine.
>
>
>>The xadd is emitted for th...
2010 Feb 16
0
[LLVMdev] Botched Build
...is Lattner wrote:
> >> On Feb 15, 2010, at 1:04 PM, David Greene wrote:
> >>>> FWIW, this is because you broke the encoding of an instruction in your
> >>>> patch. This is incorrect:
> >>>>
> >>>> +def MOVNTDQ_64mr : PSI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst,
> >>>> VR128:$src), + "movntdq\t{$src, $dst|$dst, $src}",
> >>>> + [(alignednontemporalstore (v2f64 VR128:$src),
> >>>> addr:$dst)]>;
> >>>>
> >>>&g...