Displaying 2 results from an estimated 2 matches for "mrm_d6".
Did you mean:
arm_26
2014 Jul 23
2
[LLVMdev] LowerINTRINSIC_W_CHAIN in X86
Hi guys,
In X86ISelLowering.cpp
I saw”
...
case Intrinsic::x86_rdrand_16:
case Intrinsic::x86_rdrand_32:
….
case Intrinsic::x86_avx512_gather_qpd_512:
case Intrinsic::x86_avx512_gather_qps_512:
..
“
those intrinsics are handled by “LowerINTRINSIC_W_CHAIN”.
How the “INTRINSIC_W_CHAIN” opCode is set instead of “INTRINSIC_WO_CHAIN”?
tks
Kevin
-------------- next part --------------
An
2014 Jul 23
2
[LLVMdev] LowerINTRINSIC_W_CHAIN in X86
...ltin_ia32_xtest">,
Intrinsic<[llvm_i32_ty], [], []>;
“
"def X86xtest: SDNode<"X86ISD::XTEST", SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>,
[SDNPHasChain, SDNPSideEffect]>;
“
let Defs = [EFLAGS] in
def XTEST : I<0x01, MRM_D6, (outs), (ins),
"xtest", [(set EFLAGS, (X86xtest))]>, TB, Requires<[HasTSX]>;
which CALL makes the “Intrinsic::x86_xtest” is caught under “INTRINSIC_W_CHAIN”? feel I missed something, but did not figure out.
tks
kevin
On Jul 23, 2014, at 1:16 PM, Anton Korobey...