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2016 Dec 22
1
Spill hoisting on RAL: looking for some debugging ideas
...r STbo %vreg19, <fi#0>
Result just prior to rewriting:
20B STbo %vreg19, <fi#0>
24B STbo %vreg19<kill>, <fi#0>
---
Original code is like this:
int foo(int fst, int snd, int *links) {
int ptr;
for (ptr = fst; ptr != 0; ptr = links[ptr])
mrglist();
for (ptr = snd; ptr != 0; ptr = links[ptr])
cpylist();
}
Without spill hoisting, it spills links in each loop separately into
fi#0, but with it, it moves both spills up. In architectures like
AARCH64 there are a plenty of callee-saved registers and this bug can
not be easily reproduced, s...