Displaying 6 results from an estimated 6 matches for "mpllp".
2017 Nov 27
1
[PATCH V3 10/29] drm/nouveau: deprecate pci_get_bus_and_slot()
...hw.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/hw.c
@@ -216,12 +216,15 @@
{
struct nvkm_pll_vals pllvals;
int ret;
+ int domain;
+
+ domain = pci_domain_nr(dev->pdev->bus);
if (plltype == PLL_MEMORY &&
(dev->pdev->device & 0x0ff0) == CHIPSET_NFORCE) {
uint32_t mpllP;
-
- pci_read_config_dword(pci_get_bus_and_slot(0, 3), 0x6c, &mpllP);
+ pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 3),
+ 0x6c, &mpllP);
mpllP = (mpllP >> 8) & 0xf;
if (!mpllP)
mpllP = 4;
@@ -232,7 +235,8 @@
(dev->pdev->device &...
2017 Dec 19
1
[PATCH V4 09/26] drm/nouveau: deprecate pci_get_bus_and_slot()
...hw.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/hw.c
@@ -216,12 +216,15 @@
{
struct nvkm_pll_vals pllvals;
int ret;
+ int domain;
+
+ domain = pci_domain_nr(dev->pdev->bus);
if (plltype == PLL_MEMORY &&
(dev->pdev->device & 0x0ff0) == CHIPSET_NFORCE) {
uint32_t mpllP;
-
- pci_read_config_dword(pci_get_bus_and_slot(0, 3), 0x6c, &mpllP);
+ pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 3),
+ 0x6c, &mpllP);
mpllP = (mpllP >> 8) & 0xf;
if (!mpllP)
mpllP = 4;
@@ -232,7 +235,8 @@
(dev->pdev->device &...
2017 Nov 22
0
[PATCH 10/30] drm/nouveau: deprecate pci_get_bus_and_slot()
...git a/drivers/gpu/drm/nouveau/dispnv04/hw.c b/drivers/gpu/drm/nouveau/dispnv04/hw.c
index b985990..4b35093 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/hw.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/hw.c
@@ -221,7 +221,8 @@
(dev->pdev->device & 0x0ff0) == CHIPSET_NFORCE) {
uint32_t mpllP;
- pci_read_config_dword(pci_get_bus_and_slot(0, 3), 0x6c, &mpllP);
+ pci_read_config_dword(pci_get_domain_bus_and_slot(0, 0, 3),
+ 0x6c, &mpllP);
mpllP = (mpllP >> 8) & 0xf;
if (!mpllP)
mpllP = 4;
@@ -232,7 +233,8 @@
(dev->pdev->device & 0xf...
2017 Nov 22
0
[PATCH V2 10/29] drm/nouveau: deprecate pci_get_bus_and_slot()
...hw.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/hw.c
@@ -216,12 +216,15 @@
{
struct nvkm_pll_vals pllvals;
int ret;
+ u32 domain;
+
+ domain = pci_domain_nr(dev->pdev->bus);
if (plltype == PLL_MEMORY &&
(dev->pdev->device & 0x0ff0) == CHIPSET_NFORCE) {
uint32_t mpllP;
-
- pci_read_config_dword(pci_get_bus_and_slot(0, 3), 0x6c, &mpllP);
+ pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 3),
+ 0x6c, &mpllP);
mpllP = (mpllP >> 8) & 0xf;
if (!mpllP)
mpllP = 4;
@@ -232,7 +235,8 @@
(dev->pdev->device &...
2017 Nov 27
0
[PATCH V3 10/29] drm/nouveau: deprecate pci_get_bus_and_slot()
...@ -216,12 +216,15 @@
> {
> struct nvkm_pll_vals pllvals;
> int ret;
> + int domain;
> +
> + domain = pci_domain_nr(dev->pdev->bus);
>
> if (plltype == PLL_MEMORY &&
> (dev->pdev->device & 0x0ff0) == CHIPSET_NFORCE) {
> uint32_t mpllP;
> -
> - pci_read_config_dword(pci_get_bus_and_slot(0, 3), 0x6c, &mpllP);
> + pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 3),
> + 0x6c, &mpllP);
> mpllP = (mpllP >> 8) & 0xf;
> if (!mpllP)
> mpllP = 4;
> @@ -232,7 +235,...
2017 Jan 20
0
[PATCH] nv1a,nv1f/disp: fix memory clock rate retrieval
...2 insertions(+), 1 deletion(-)
diff --git a/drm/nouveau/dispnv04/hw.c b/drm/nouveau/dispnv04/hw.c
index 48ad4be..b985990 100644
--- a/drm/nouveau/dispnv04/hw.c
+++ b/drm/nouveau/dispnv04/hw.c
@@ -222,6 +222,7 @@ nouveau_hw_get_clock(struct drm_device *dev, enum nvbios_pll_type plltype)
uint32_t mpllP;
pci_read_config_dword(pci_get_bus_and_slot(0, 3), 0x6c, &mpllP);
+ mpllP = (mpllP >> 8) & 0xf;
if (!mpllP)
mpllP = 4;
@@ -232,7 +233,7 @@ nouveau_hw_get_clock(struct drm_device *dev, enum nvbios_pll_type plltype)
uint32_t clock;
pci_read_config_dword(pci_get_bu...