search for: mpidr

Hi, This is the fifth version of this patch series. With the Versatile Express TC2, it''s possible to boot only with A7 or A15. If the user choose to boot with only A7, the CPU ID will start at 0x100. As Xen relies on it to set the logical ID and the GIC, it won''t be possible to use Xen with this use case. This patch series is divided in 3 parts: - Patch 1: prepare Xen

Dear all, in the past I have been able to access websites with data directly. For example the following code works nicely mydata <- read.table("http://www.lifetable.de/data/MPIDR/POL_2004.txt", header=TRUE) But what happens if I need a username and password (a different site)? How do I do that? Or is it not possible to this in R? I tried something like this mydata.frame <- read.table("myusr:mypswd at www.mydata.com/adir/afile.txt") but it did not work...

...>> +{ >> + return false; >> +} >> + >> +static inline void kvm_update_pvlock_preempted(struct kvm_vcpu *vcpu, u64 preempted) >> +{ >> +} >> + >> void kvm_mmu_wp_memory_region(struct kvm *kvm, int slot); >> >> struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr); >> diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h >> index c61260cf63c5..d9b2a21a87ac 100644 >> --- a/arch/arm64/include/asm/kvm_host.h >> +++ b/arch/arm64/include/asm/kvm_host.h >> @@ -...

...; instruction cache > [ 0.000000] PERCPU: Embedded 12 pages/cpu @ee5c0000 s19916 r8192 d21044 > u49152 > [ 0.000000] RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2. > [ 0.004932] CPU: Testing write buffer coherency: ok > [ 0.046656] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000 > [ 0.052951] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001 > [ 0.053072] Brought up 2 CPUs > [ 0.053106] CPU: All CPU(s) started in HYP mode. > [ 0.053111] CPU: Virtualization extensions available. > [ 1.572315] ledtrig-cpu: registered to indicate activity...

From: Zengruan Ye <yezengruan at huawei.com> This patch set aims to support the vcpu_is_preempted() functionality under KVM/arm64, which allowing the guest to obtain the vcpu is currently running or not. This will enhance lock performance on overcommitted hosts (more runnable vcpus than physical cpus in the system) as doing busy waits for preempted vcpus will hurt system performance far

From: Zengruan Ye <yezengruan at huawei.com> This patch set aims to support the vcpu_is_preempted() functionality under KVM/arm64, which allowing the guest to obtain the vcpu is currently running or not. This will enhance lock performance on overcommitted hosts (more runnable vcpus than physical cpus in the system) as doing busy waits for preempted vcpus will hurt system performance far

This patch set aims to support the vcpu_is_preempted() functionality under KVM/arm64, which allowing the guest to obtain the VCPU is currently running or not. This will enhance lock performance on overcommitted hosts (more runnable VCPUs than physical CPUs in the system) as doing busy waits for preempted VCPUs will hurt system performance far worse than early yielding. We have observed some

...68] pid_max: default: 32768 minimum: 301 [ 0.000416] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes) [ 0.000421] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes) [ 0.000655] CPU: Testing write buffer coherency: ok [ 0.000769] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000 [ 0.000899] Setting up static identity map for 0x100000 - 0x100060 [ 0.000972] mvebu-soc-id: MVEBU SoC ID=0x6828, Rev=0x4 [ 0.001046] mvebu-pmsu: Initializing Power Management Service Unit [ 0.001095] Hierarchical SRCU implementation. [ 0.002554] smp: Bringing up secondary C...

...60] pid_max: default: 32768 minimum: 301 [ 0.000407] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes) [ 0.000413] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes) [ 0.000648] CPU: Testing write buffer coherency: ok [ 0.000761] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000 [ 0.000889] Setting up static identity map for 0x100000 - 0x100060 [ 0.000962] mvebu-soc-id: MVEBU SoC ID=0x6828, Rev=0x4 [ 0.001034] mvebu-pmsu: Initializing Power Management Service Unit [ 0.001082] Hierarchical SRCU implementation. [ 0.002449] smp: Bringing up secondary C...

George has release acked all of these. Otherwise mostly minor updates this time around. Summary: A == acked, M == modified A xen: arm64: Add 8250 earlyprintk support A xen: arm64: Add Basic Platform support for APM X-Gene Storm. A xen: arm64: Add APM implementor id to processor implementers. M xen: arm: add a quirk to handle platforms with unusual GIC layout A xen: arm: allow platform

Hi Ben, Thanks for your reply. My replies follow in between. Luís On Thu, Jan 25, 2018 at 5:40 AM, Ben Skeggs <skeggsb at gmail.com> wrote: > On 24 January 2018 at 06:19, Luís Mendes <luis.p.mendes at gmail.com> wrote: >> Hi Arnd, >> >> Sorry for sending this email directly to you, but maybe you can help >> me, or guide me where to look for. >>

...[0001.324] Interrupts Init done [0001.327] calling constructors [0001.331] initializing heap [0001.333] initializing threads [0001.336] initializing timers [0001.339] creating bootstrap completion thread [0001.344] top of bootstrap2() [0001.347] CPU: ARM Cortex A57 [0001.350] CPU: MIDR: 0x411FD073, MPIDR: 0x80000100 [0001.355] initializing platform [0001.358] I> Boot-device: eMMC [0001.362] I> odm data is 1090000 [0001.365] I> Reading GPT from 512 for device 00000003 [0001.371] I> Reading GPT from 8388096 for device 00000003 [0001.377] I> Found 6 partitions in 00000003 device [0001.3...

This round implements all of the review comments from V2 and all patches are now acked. Unless there are any objections I intend to apply later this morning. Ian.

This patch series implements SMP boot for arch/arm, as far as getting all CPUs up and running the idle loop. Changes from v1: - moved barriers out of loop in udelay() - dropped broken GIC change in favour of explanatory comment - made the increment of ready_cpus atomic (I couldn''t move the increment to before signalling the next CPU because the PT switch has to happen between

I''m afraid this series is rather a grab bag and it is distressingly large at this stage. With this series I can boot an Xgene board until it fails to find its SATA controller. This is a dom0 issue for which patches are pending from APM (/me nudges Anup). As well as the APM specific platform stuff there are also some generic improvements which were either necessary or useful during this

...[0001.304] Interrupts Init done [0001.307] calling constructors [0001.310] initializing heap [0001.313] initializing threads [0001.316] initializing timers [0001.319] creating bootstrap completion thread [0001.323] top of bootstrap2() [0001.327] CPU: ARM Cortex A57 [0001.330] CPU: MIDR: 0x411FD073, MPIDR: 0x80000100 [0001.335] initializing platform [0001.338] I> Boot-device: eMMC [0001.341] I> odm data is 1090000 [0001.345] I> Reading GPT from 512 for device 00000003 [0001.350] I> Reading GPT from 8388096 for device 00000003 [0001.357] I> Found 6 partitions in 00000003 device [0001.3...

...[0001.300] Interrupts Init done [0001.304] calling constructors [0001.307] initializing heap [0001.309] initializing threads [0001.312] initializing timers [0001.316] creating bootstrap completion thread [0001.320] top of bootstrap2() [0001.323] CPU: ARM Cortex A57 [0001.326] CPU: MIDR: 0x411FD073, MPIDR: 0x80000100 [0001.331] initializing platform [0001.335] I> Boot-device: eMMC [0001.338] I> odm data is 1090000 [0001.341] I> Reading GPT from 512 for device 00000003 [0001.347] I> Reading GPT from 8388096 for device 00000003 [0001.353] I> Found 6 partitions in 00000003 device [0001.3...

First off, Apologies for the massive patch series... This series boots a 32-bit dom0 kernel to a command prompt on an ARMv8 (AArch64) model. The kernel is the same one as I am currently using with the 32 bit hypervisor I haven''t yet tried starting a guest or anything super advanced like that ;-). Also there is not real support for 64-bit domains at all, although in one or two places I