search for: mp_ioapic

...O_APIC_reg_03 reg_03; - unsigned long flags; - - if (apic_verbosity == APIC_QUIET) - return; - - printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); - for (i = 0; i < nr_ioapics; i++) - printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", - mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]); - - /* - * We are a bit conservative about what we expect. We have to - * know about every hardware change ASAP. - */ - printk(KERN_INFO "testing the IO APIC.......................\n"); - - for (apic = 0; apic < nr_ioapics; apic++) { - - spi...

...O_APIC_reg_03 reg_03; - unsigned long flags; - - if (apic_verbosity == APIC_QUIET) - return; - - printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); - for (i = 0; i < nr_ioapics; i++) - printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", - mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]); - - /* - * We are a bit conservative about what we expect. We have to - * know about every hardware change ASAP. - */ - printk(KERN_INFO "testing the IO APIC.......................\n"); - - for (apic = 0; apic < nr_ioapics; apic++) { - - spi...

...7 +18,6 @@ extern const struct genapic apic_summit; extern const struct genapic apic_bigsmp; -extern const struct genapic apic_default; const struct genapic *__read_mostly genapic; --- 2011-03-09.orig/xen/arch/x86/io_apic.c +++ 2011-03-09/xen/arch/x86/io_apic.c @@ -2491,8 +2491,6 @@ void dump_ioapic_irq_info(void) } } -unsigned highest_gsi(void); - static unsigned int __initdata max_gsi_irqs; integer_param("max_gsi_irqs", max_gsi_irqs); --- 2011-03-09.orig/xen/arch/x86/mpparse.c +++ 2011-03-09/xen/arch/x86/mpparse.c @@ -21,7 +21,6 @@ #include <xen/delay.h> #includ...

...Linux upon encountering the same kind of system. Signed-off-by: Jan Beulich <jbeulich@suse.com> --- a/xen/arch/x86/domain_build.c +++ b/xen/arch/x86/domain_build.c @@ -1114,7 +1114,7 @@ int __init construct_dom0( for ( i = 0; i < nr_ioapics; i++ ) { mfn = paddr_to_pfn(mp_ioapics[i].mpc_apicaddr); - if ( smp_found_config ) + if ( !rangeset_contains_singleton(mmio_ro_ranges, mfn) ) rc |= iomem_deny_access(dom0, mfn, mfn); } --- a/xen/arch/x86/io_apic.c +++ b/xen/arch/x86/io_apic.c @@ -2468,6 +2468,9 @@ void __init init_ioapic_mappings(void)...

...rn("At line %d, gsi_base is %d\n", __LINE__,gsi_base); 1: x/i $pc => 0xc1046a64 <mp_register_ioapic+180>: mov    %edi,0xc(%esp) 2: gsi_base = 0 (gdb) p/x 0xc+$esp $1 = 0xc1b2fe34 (gdb) disp *(int *)0xc1b2fe34 3: *(int *)0xc1b2fe34 = 120 (gdb) ni 414 ioapics[idx].mp_config.type = MP_IOAPIC; 1: x/i $pc => 0xc1046a68 <mp_register_ioapic+184>: imul   $0x2c,%ebx,%edi 2: gsi_base = 0 3: *(int *)0xc1b2fe34 = 0 (gdb)  0xc1046a6b 414 ioapics[idx].mp_config.type = MP_IOAPIC; 1: x/i $pc => 0xc1046a6b <mp_register_ioapic+187>: movb   $0x2,-0x3e2cb1bc(%edi) 2: gsi_base = 0 3:...

On Fri, 2018-02-09 at 10:36 +0000, David Woodhouse wrote: > > Did you get anywhere with the function attribute? Having isolated the > next boot failure to "it goes away if I compile io_apic.c without > retpoline", bisecting it per-function would help to further delay the > bit where I actually have to start *thinking*... It's mp_register_ioapic(), and only when

...i_base); > 1: x/i $pc > => 0xc1046a64 <mp_register_ioapic+180>: mov %edi,0xc(%esp) > 2: gsi_base = 0 > (gdb) p/x 0xc+$esp > $1 = 0xc1b2fe34 > (gdb) disp *(int *)0xc1b2fe34 > 3: *(int *)0xc1b2fe34 = 120 > (gdb) ni > 414 ioapics[idx].mp_config.type = MP_IOAPIC; > 1: x/i $pc > => 0xc1046a68 <mp_register_ioapic+184>: imul $0x2c,%ebx,%edi > 2: gsi_base = 0 > 3: *(int *)0xc1b2fe34 = 0 > (gdb) > 0xc1046a6b 414 ioapics[idx].mp_config.type = MP_IOAPIC; > 1: x/i $pc > => 0xc1046a6b <mp_register_ioapic+187...

..."can not resume ioapic due to lack of memory\n"); + return 1; + } + + entry = ioapic_pm_state; + + spin_lock_irqsave(&ioapic_lock, flags); + for (apic = 0; apic < nr_ioapics; apic++){ + reg_00.raw = io_apic_read(apic, 0); + if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid) { + reg_00.bits.ID = mp_ioapics[apic].mpc_apicid; + io_apic_write(apic, 0, reg_00.raw); + } + for (i = 0; i < nr_ioapic_registers[apic]; i ++, entry ++ ) { + io_apic_write(apic, 0x11+2*i, *(((int *)entry)+1)); + io_apic...

1: IOMMU: properly check whether interrupt remapping is enabled 2: AMD IOMMU: only disable when certain IVRS consistency checks fail 3: VT-d: deal with 5500/5520/X58 errata Patch 1 and 2 are version 2 of a previously submitted, then withdrawn patch following up after XSA-36. Patch 3 is version 3 of a patch previously sent by Malcolm and Andrew. Signed-off-by: Jan Beulich

Hi Ingo, Here''s the chunk of patches to add Xen Dom0 support (it''s probably worth creating a new xen/dom0 topic branch for it). A dom0 Xen domain is basically the same as a normal domU domain, but it has extra privileges to directly access hardware. There are two issues to deal with: - translating to and from the domain''s pseudo-physical addresses and real machine