Displaying 10 results from an estimated 10 matches for "movzx32rr8".
2017 Aug 02
3
[InstCombine] Simplification sometimes only transforms but doesn't simplify instruction, causing side effect in other pass
...information is not ready in both places.
* The pattern matching looks quite ad hoc on machine IR. I need to
figure out we can replace %vreg0 in "AND32ri8 %vreg0<tied0>, 31" with
%vreg1 by looking at the copy chain starting from %vreg9<def> = COPY
%vreg0 to %vreg1<def> = MOVZX32rr8 %vreg9 first, and at the same time,
after replacing vreg0 with %vreg1, vreg0 becomes dead at the other
AND32ri and we can save an instruction there. In addition, replace
%vreg0 with %vreg1 may increase an extra move before "AND32ri8
%vreg0<tied0>, 31", so we still need to check &quo...
2017 Aug 02
3
[InstCombine] Simplification sometimes only transforms but doesn't simplify instruction, causing side effect in other pass
...;>
>> * The pattern matching looks quite ad hoc on machine IR. I need to
>> figure out we can replace %vreg0 in "AND32ri8 %vreg0<tied0>, 31" with
>> %vreg1 by looking at the copy chain starting from %vreg9<def> = COPY
>> %vreg0 to %vreg1<def> = MOVZX32rr8 %vreg9 first, and at the same time,
>> after replacing vreg0 with %vreg1, vreg0 becomes dead at the other
>> AND32ri and we can save an instruction there. In addition, replace
>> %vreg0 with %vreg1 may increase an extra move before "AND32ri8
>> %vreg0<tied0>, 31&q...
2011 Jun 05
1
[LLVMdev] MachineSink and EFLAGS
...g2,%vreg0
> CMP8mi <fi#-1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[FixedStack-1](align=8)
> %vreg3<def> = CMOV_GR8 %vreg2<kill>, %vreg1<kill>, 4, %EFLAGS<imp-def,dead>, %EFLAGS<imp-use>; GR8:%vreg3,%vreg2,%vreg1
> %vreg4<def> = MOVZX32rr8 %vreg3<kill>; GR32:%vreg4 GR8:%vreg3
> %EAX<def> = COPY %vreg4; GR32:%vreg4
> RET
>
> CMOV_GR8 instruction has EFLAGS use which is not marked kill, and that's why EFLAGS is marked live-in in the new blocks created when lowering the pseudo cmov. But besides that it als...
2009 Mar 17
0
[LLVMdev] Overlapping register classes
On Mar 16, 2009, at 11:31 AM, Jakob Stoklund Olesen wrote:
> Dan Gohman <gohman at apple.com> writes:
>
>> On Mar 15, 2009, at 2:02 PM, Jakob Stoklund Olesen wrote:
>>> Am I misusing register classes, or is this simply functionality that
>>> has not been written yet? The existing backends seem to have only
>>> one
>>> register class per
2009 Apr 22
2
[LLVMdev] Def/Kill flags for subregisters
...MOV32rm %ESP, 1, %noreg, 8, %noreg, Mem:LD(4,4)
[FixedStack-2 + 0]
%ECX<def> = MOV32rm %ESP, 1, %noreg, 4, %noreg, Mem:LD(4,16)
[FixedStack-1 + 0]
%EDX<def> = LEA32r %ECX, 1, %EAX, 0
%EDX<def> = ADD32rr %EDX, %EAX<kill>, %EFLAGS<imp-def,dead>
%EAX<def> = MOVZX32rr8 %CL<kill>
%EAX<def> = ADD32rr %EAX, %EDX<kill>, %EFLAGS<imp-def,dead>
RET %EAX<imp-use,kill>
This function defines ECX and kills CL, leaving ECX, CX, and CH still
alive. It is not a problem here because ECX is not reused, but I think
that if it were reused, it...
2011 Jun 05
0
[LLVMdev] MachineSink and EFLAGS
...d>; GR8:%vreg2,%vreg0
CMP8mi <fi#-1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[FixedStack-1](align=8)
%vreg3<def> = CMOV_GR8 %vreg2<kill>, %vreg1<kill>, 4, %EFLAGS<imp-def,dead>, %EFLAGS<imp-use>; GR8:%vreg3,%vreg2,%vreg1
%vreg4<def> = MOVZX32rr8 %vreg3<kill>; GR32:%vreg4 GR8:%vreg3
%EAX<def> = COPY %vreg4; GR32:%vreg4
RET
CMOV_GR8 instruction has EFLAGS use which is not marked kill, and that's why EFLAGS is marked live-in in the new blocks created when lowering the pseudo cmov. But besides that it also has an imp-def of...
2009 Mar 16
2
[LLVMdev] Overlapping register classes
Dan Gohman <gohman at apple.com> writes:
> On Mar 15, 2009, at 2:02 PM, Jakob Stoklund Olesen wrote:
>> Am I misusing register classes, or is this simply functionality that
>> has not been written yet? The existing backends seem to have only one
>> register class per machine value type.
>
> The x86 backend has an example of a partial solution. The GR32
>
2011 Jun 03
2
[LLVMdev] MachineSink and EFLAGS
On Jun 3, 2011, at 2:59 AM, Galanov, Sergey wrote:
> Hi, Bill and Jakob.
>
> I don't quite understand. I am talking about CMOV_GR* instructions which are conservatively marked as clobbering EFLAGS in X86InstrCompiler.td. Doesn't that mean there cannot be any use of EFLAGS in subsequent instructions before it is defined by some other instruction?
>
> I also don't
2017 Aug 02
2
[InstCombine] Simplification sometimes only transforms but doesn't simplify instruction, causing side effect in other pass
...in both places.
>
> * The pattern matching looks quite ad hoc on machine IR. I need to
> figure out we can replace %vreg0 in "AND32ri8 %vreg0<tied0>, 31" with
> %vreg1 by looking at the copy chain starting from %vreg9<def> = COPY
> %vreg0 to %vreg1<def> = MOVZX32rr8 %vreg9 first, and at the same time,
> after replacing vreg0 with %vreg1, vreg0 becomes dead at the other
> AND32ri and we can save an instruction there. In addition, replace
> %vreg0 with %vreg1 may increase an extra move before "AND32ri8
> %vreg0<tied0>, 31", so we stil...
2009 Apr 22
0
[LLVMdev] Def/Kill flags for subregisters
...8, %noreg, Mem:LD(4,4)
> [FixedStack-2 + 0]
> %ECX<def> = MOV32rm %ESP, 1, %noreg, 4, %noreg, Mem:LD(4,16)
> [FixedStack-1 + 0]
> %EDX<def> = LEA32r %ECX, 1, %EAX, 0
> %EDX<def> = ADD32rr %EDX, %EAX<kill>, %EFLAGS<imp-def,dead>
> %EAX<def> = MOVZX32rr8 %CL<kill>
> %EAX<def> = ADD32rr %EAX, %EDX<kill>, %EFLAGS<imp-def,dead>
> RET %EAX<imp-use,kill>
>
> This function defines ECX and kills CL, leaving ECX, CX, and CH still
> alive. It is not a problem here because ECX is not reused, but I think
> th...