Displaying 9 results from an estimated 9 matches for "movz".
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2016 Jan 15
3
Help handling opaque AArch64 immediates
Hello LLVM,
I'm playing with a new ISD::OPAQUE instruction to make hoisting first
class and eliminate a lot of tweaky flag setting/checking around
opaque constants. It's going well for the IR and x86, but I now I
need to sort out details for all the other targets.
To start, can someone please advise on the AAarch64 equivalent of
these X86 patterns?
// Opaque values become mov immediate
2014 Jun 20
2
[LLVMdev] [AArch64] Question about far call
...e
I got an error from ld:
a.c:(.text+0x8): relocation truncated to fit: R_AARCH64_CALL26 against
symbol `foo' define in *ABS* section in a.exe
The question is: do I miss some options or pragmas during compilation ?
Should I expect llvm to emit the following code?
movz x8, #:abs_g3:foo
movk x8, #:abs_g2_nc:foo
movk x8, #:abs_g1_nc:foo
movk x8, #:abs_g0_nc:foo
ldr x8, [x8]
blr x8
or I miss some flag during linking?
PS. The above test works...
2018 Sep 13
2
[GlobalISel][MIPS] Legality and instruction combining
... %4:_(s1) = G_ICMP intpred(sgt), %0(s32), %1
%5:_(s32) = G_SELECT %4(s1), %2, %3
On mips 32, integer compare uses i32 as result and that result is zero extended.
For G_SELECT, we will select instructions that check whether "test register" was zero or not (selected instructions are movz or movn).
Test register has size 32, having that in mind, idealy, legalizer should produce
%4:_(s32) = G_ICMP intpred(sgt), %0(s32), %1
%5:_(s32) = G_SELECT %4(s32), %2, %3
after combining all extends and truncs.
Currently, it is not possible to widen test register (type 1) in G_SELECT a...
2015 Aug 11
2
NSW and ExtLdPromotion()
...ine i64 @foo(i32* nocapture readonly %a) #0 {
entry:
%0 = load i32* %a, align 4, !tbaa !1
%conv = sext i32 %0 to i64
%mul = mul nsw i64 %conv, 1405
ret i64 %mul
}
This promotion itself looks fine to me if nsw is true, and the final code
becomes:
ldrsw x8, [x0]
movz w9, #0x57d
mul x0, x8, x9
ret
The results is different from a 32-bit mul then sext, at least for my
testcase.
Without nsw, ExtLdPromotion() didn't change anything, and the result is
correct.
Any thoughts would be helpful.
Regards
Lawrence Hu...
2013 Oct 15
0
[LLVMdev] [llvm-commits] r192750 - Enable MI Sched for x86.
...iginal)
>> +++ llvm/trunk/test/CodeGen/X86/3addr-16bit.ll Tue Oct 15 18:33:07 2013
>> @@ -34,7 +34,8 @@ entry:
>>
>> ; 64BIT-LABEL: t2:
>> ; 64BIT-NOT: movw %si, %ax
>> -; 64BIT: leal -1(%rsi), %eax
>> +; 64BIT: decl %eax
>> +; 64BIT: movzwl %ax
>> %0 = icmp eq i16 %k, %c ; <i1> [#uses=1]
>> %1 = add i16 %k, -1 ; <i16> [#uses=3]
>> br i1 %0, label %bb, label %bb1
>> @@ -58,7 +59,7 @@ entry:
>>
>> ; 64BIT-LABEL: t3:
>>...
2013 Oct 03
1
[LLVMdev] Help with a Microblaze code generation problem.
...p)
sw $zero, 8($fp)
lui $1, 32768
sw $1, 0($fp)
sw $zero, 4($fp)
lw $2, 8($fp)
xor $1, $2, $1
addiu $3, $zero, -1
slt $2, $3, $2
lw $3, 12($fp)
sltiu $3, $3, 1
movz $2, $3, $1
move $sp, $fp
lw $fp, 20($sp)
addiu $sp, $sp, 24
jr $ra
nop
signed long long:
main:
.frame $fp,24,$ra
.mask 0x40000000,-4
.fmask 0x00000000,0
.set noreorder
.set nomac...
2018 Sep 01
3
Clang for the PlayStation 2
..."I/O Processor" (IOP),
which is used for PS1 compatibility and for I/O.
The EE is based on a custom chip called the R5900, which implements most of
MIPS III (except the ll and sc instructions, which make little sense on a
single-core CPU), as well as some instructions from MIPS IV (pref,
movz/movn, rsqrt.s), and a set of SIMD instructions known as Multimedia
Instructions (MMI). It also contains a non-IEEE 754 single-precision FPU
(which has provided a lot of headaches). It was later re-used by Toshiba as
the TX79, along with a proper FPU.
The IOP is based on the MIPS I R3051A, and was...
2018 May 10
2
[RFC] MC support for variant scheduling classes.
...strInfo.cpp:
```
// Return true if this instruction simply sets its single destination
register
// to zero. This is equivalent to a register rename of the zero-register.
bool AArch64InstrInfo::isGPRZero(const MachineInstr &MI) {
switch (MI.getOpcode()) {
default:
break;
case AArch64::MOVZWi:
case AArch64::MOVZXi: // movz Rd, #0 (LSL #0)
if (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) {
assert(MI.getDesc().getNumOperands() == 3 &&
MI.getOperand(2).getImm() == 0 && "invalid MOVZi operands");
return true;...
2005 Apr 02
1
[PATCH] VMX support for MMIO/PIO in VM8086 mode
...return value.
mpci_p->mmio_target = mmio_inst.operand[1] | WZEROEXTEND;
- send_mmio_req(gpa, &mmio_inst, 0, 1, 0);
+ send_mmio_req(gpa, &mmio_inst, 0, IOREQ_READ, 0);
return ;
} else {
printk("handle_mmio - EXIT: movz error!\n");
@@ -515,10 +580,32 @@
}
if (!strncmp((char *)mmio_inst.i_name, "movs", 4)) {
- int tmp_dir;
+ unsigned long addr = 0;
+ int dir;
- tmp_dir = ((va == inst_decoder_regs->edi) ? IOREQ_WRITE : IOREQ_READ);
- send_mmio_req(gpa, &mmio_i...