search for: movw

On Wed, Nov 1, 2017 at 12:51 PM, Karol Herbst <kherbst at redhat.com> wrote: > fixes compilation issues with recent envytools, because movw was removed > from fuc5, because it doesn't exist there anymore. The current code is > most likely broken for fuc5 hardware as well and might have triggered all > kinds of random memory reclocking fails. > > Changes in fuc3 binaries are tue do opcode optimizations using shorter &...

fixes compilation issues with recent envytools, because movw was removed from fuc5, because it doesn't exist there anymore. The current code is most likely broken for fuc5 hardware as well and might have triggered all kinds of random memory reclocking fails. Changes in fuc3 binaries are tue do opcode optimizations using shorter opcodes when possible. S...

...c: + .space 512 /* set 512 bytes to zero. doc: 7.102 */ + + .text + .global _start +_start: + + /* All code from here until the relocation operation does nothing that relies */ + /* on the value of the instruction pointer */ + cli /* disable interrupts */ + xorw %ax, %ax /* reset to 0 */ + movw %ax, %ds /* reset data segment base */ + movw %ax, %ss /* reset stack segment base */ + movw $stack, %sp /* set stack pointer */ + movw %sp, %si /* address where BIOS loaded MBR, used as source address for relocation */ + pushw %es /* save Plug'n'Play header provided by BIOS in ES:DI...

...truction operands for any special encoding needs, including registering fixups, using the EncoderMethod string. For an example, have a look at the LDRi12 instruction and how it registers a fixup for the addrmode_imm12 operand when it needs one. Hi Jim,. follow up question for ya: The current movt/movw pair (as defined in ARMInstrInfo.td) does not use EncoderMethod string to declare a special case handler. At the current time, for the assembly printing, MCAsmStreamer::EmitInstruction(const MCInst &Inst) calls out to MCExpr::print(raw_ostream &OS) which then calls out to MCSymbolRe...

...c: + .space 512 /* set 512 bytes to zero. doc: 7.102 */ + + .text + .global _start +_start: + + /* All code from here until the relocation operation does nothing that relies */ + /* on the value of the instruction pointer */ + cli /* disable interrupts */ + xorw %ax, %ax /* reset to 0 */ + movw %ax, %ds /* reset data segment base */ + movw %ax, %ss /* reset stack segment base */ + movw $stack, %sp /* set stack pointer */ + movw %sp, %si /* address where BIOS loaded MBR, used as source address for relocation */ + movw %sp, %bp /* needed later if drive number is to be forced due to Ctr...

...c: + .space 512 /* set 512 bytes to zero. doc: 7.102 */ + + .text + .global _start +_start: + + /* All code from here until the relocation operation does nothing that relies */ + /* on the value of the instruction pointer */ + cli /* disable interrupts */ + xorw %ax, %ax /* reset to 0 */ + movw %ax, %ds /* reset data segment base */ + movw %ax, %ss /* reset stack segment base */ + movw $stack, %sp /* set stack pointer */ + movw %sp, %si /* address where BIOS loaded MBR, used as source address for relocation */ + pushw %es /* save Plug'n'Play header provided by BIOS in ES:DI...

.../fuc/macros.fuc b/drm/nouveau/nvkm/subdev/pmu/fuc/macros.fuc > index 0d5cbeb..bb59eb4 100644 > --- a/drm/nouveau/nvkm/subdev/pmu/fuc/macros.fuc > +++ b/drm/nouveau/nvkm/subdev/pmu/fuc/macros.fuc > @@ -252,12 +252,12 @@ > #endif > > #define st(size, addr, reg) /* > -*/ movw $r0 addr /* > +*/ mov $r0 addr /* First of all, I know it is annoying, but we *need* to understand exactly what movw is now doing. Secondly, I seem to remember that a 32 bit mov was not added until fuc3 or something. Have you tried assembling this code on older fuc versions? Pretty sure it...

...lues of ES, DI, the contents of [ES:DI] (4 bytes), scans memory for * $PnP then reports a boot failure. * * This should (hopefully) be only 8086 code */ // #define DEBUG_MARKER1 /* Insert markers in binary */ // #define DEBUG_START /* Print entry addresses at start */ // #define DEBUG_LOADE /* movw versus pop */ #define DEBUG_PNP /* Scan for $PnP and show address */ #define DEBUG_PAK /* Press Any Key before boot fail */ #ifdef DEBUG_MARKER1 .macro ASCII_MARKER1 s:vararg .ascii \s .endm #else /* DEBUG_MARKER1 */ .macro ASCII_MARKER1 s:vararg .endm #endif /* DEBUG_MARKER1 */ #ifdef DEBUG...

On 19 December 2016 at 09:58, Jojo Ma <jojo.ma at linaro.org> wrote: > /home/likewise-open/SPREADTRUM/jojo.ma/jojoma/source/llvm/llvm-linaro/llvm/llvm/test/CodeGen/Thumb2/machine-licm.ll:88:10: > error: expected string not found in input > ; CHECK: movw {{(r[0-9])|(lr)}}, #32768 > ^ > <stdin>:56:2: note: scanning from here > movw r12, #32768 > ^ Hi Jojo, This is just a bad check line. :) Instead of: ; CHECK: movw {{(r[0-9])|(lr)}}, #32768 it should have been: ; CHECK: movw {{(r[0-9]+)|(lr)}}, #32768 (ie. add the...

....fuc >>> index 0d5cbeb..bb59eb4 100644 >>> --- a/drm/nouveau/nvkm/subdev/pmu/fuc/macros.fuc >>> +++ b/drm/nouveau/nvkm/subdev/pmu/fuc/macros.fuc >>> @@ -252,12 +252,12 @@ >>> #endif >>> #define st(size, addr, reg) /* >>> -*/ movw $r0 addr /* >>> +*/ mov $r0 addr /* >> >> First of all, I know it is annoying, but we *need* to understand exactly >> what movw is now doing. >> >> Secondly, I seem to remember that a 32 bit mov was not added until fuc3 or > fuc5 Ah, right, fuc3 was on...

...vm/llvm-linaro/llvm/llvm/test/CodeGen/Thumb2/machine-licm.ll --check-prefix=PIC -- Exit Code: 1 Command Output (stderr): -- /home/likewise-open/SPREADTRUM/ jojo.ma/jojoma/source/llvm/llvm-linaro/llvm/llvm/test/CodeGen/Thumb2/machine-licm.ll:88:10: error: expected string not found in input ; CHECK: movw {{(r[0-9])|(lr)}}, #32768 ^ <stdin>:56:2: note: scanning from here movw r12, #32768 ^ The outputs before and after the canonicalisation are: - before canonicalisation _t3: @ BB#0: @ %bb.nph push {r7, lr} mov r7, sp movw lr, #32768 movs r2, #0...

Hi Borja, > Without doing what i mentioned and letting LLVM expand all operations wider > than 8 bits as you asked, the code produced is excellent supposing that many > of the moves there should be 16 bit moves reducing code size and right > register allocation, also something important for me is that the code is > better than gcc's. When i say right reg allocation it doesnt

...tions. typedef short t; extern t mcos(t a); extern t mdiv(t a, t b); t foo(t a, t b) { short p1 = mcos(b); short p2 = mcos(a); return mdiv(p1&p2, p1^p2); } This C code produces: ; a<- r25:r24 b<--r23:r22 mov r18, r24 mov r19, r25 <-- can be combined into a movw r19:r18, r25:r24 mov r25, r23 mov r24, r22 <-- can be combined into a movw r25:r24, r23:r22 call mcos ; here we have the case i was explaining, pairs dont match because they're the other way round, function result is in r25:r24 ; but it's storing the hi part in r20 i...

I believe I have now fixed the 0x64 0xa1 0x00 0x00 0x00 0x00 bug in r199364. On Wed, Jan 15, 2014 at 10:53 AM, Craig Topper <craig.topper at gmail.com>wrote: > To fix it we need to change offset8/offset16/etc to have two suboperands > and update the printer to understand that. Also update the disassembler to > add the segment to the MCInst when its creating it. When I did these

...ceed and combine two 8 bit instructions into a 16 bit one as Jeff pointed out in his email? For example i want to combine a 16 bit add like this: // b = b + 1: (b stored in r25:r24) add r24, 1 adc r25, 0 into adw r25:r24, 1 and the one im talking all my mails about move r25, r23 move r24, r22 into movw r25:r24, r23:r22 or move r18, r2 move r19, r3 into movw r19:r18, r3:r2 any combination of moves with reg pairs are valid. I wrote a function pass to test, it scanned for moves and checked if next instruction was a move to see if globally it was a 16 move and replace those 2 insts with a movw. But...

Hi everyone, happy new year. This note is to announce that support for PC relative reloc tags for movw/movt is nearing completion (hopefully <48hrs!). This work is is from Jan Voung, David Meyer and myself. Unfortunately, to test this change, we need to patch ARM/AsmParser to address http://llvm.org/bugs/show_bug.cgi?id=8721 Locally, we have hacked up a solution to 8721, but its not ideal since...

...eau/nvkm/subdev/pmu/fuc/macros.fuc >> index 0d5cbeb..bb59eb4 100644 >> --- a/drm/nouveau/nvkm/subdev/pmu/fuc/macros.fuc >> +++ b/drm/nouveau/nvkm/subdev/pmu/fuc/macros.fuc >> @@ -252,12 +252,12 @@ >> #endif >> #define st(size, addr, reg) /* >> -*/ movw $r0 addr /* >> +*/ mov $r0 addr /* > > > First of all, I know it is annoying, but we *need* to understand exactly > what movw is now doing. > > Secondly, I seem to remember that a 32 bit mov was not added until fuc3 or fuc5 > something. Have you tried assembling thi...

...mp 1f /* We have non-GPT partition information */ 2: movl 8(%si), %ecx #endif 1: /* We have no partition information */ pushl %ebx /* -4: partoffset_hi */ pushl %ecx /* -8: partoffset_lo */ pushw %es /* -10: es:di -> $PnP header */ pushw %di /* -12: es:di -> $PnP header */ movw %bp, %ds movw %bp, %es ADJUST_DRIVE pushw %dx /* -14: dl -> drive number */ /* Copy down to 0:0x600 */ movw $0x7c00, %si movw $_start, %di movw $(512/2), %cx rep; movsw ljmpw $0, $next next: /* Check to see if we have EBIOS */ pushw %dx /* drive number */ movb $0x41, %ah /* %...

Fixes failure to compile with recent envyas as a result of the 'movw' alias being removed for v5. A bit of history: v3 only has a 16-bit sign-extended immediate mov op. In order to set the high bits, there's a separate 'sethi' op. envyas validates that the value passed to mov(imm) is between -0x8000 and 0x7fff. In order to simplify macros that load...

...- Add the subtarget feature/attribute "execute-only" to the ARM code generator to enable the feature. - Add a clang option "-mexecute-only" that passes said attribute to LLVM. If execute only is enabled: - Instead of using integer literal pools, use movw/movt to construct the literals. This means this feature is only available for sub-targets that support these instructions. - For floating point literals, use movw/movt/vmov instead of a literal pool. - Move jump tables to data sections. This is basically a re-implementation...