Displaying 2 results from an estimated 2 matches for "movrdrr".
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2010 Sep 09
2
[LLVMdev] Possible missed optimization? 2.0
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URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20100909/2836177c/attachment.html>
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********** SIMPLE REGISTER COALESCING **********
********** Function: foo
********** JOINING INTERVALS ***********
entry:
4 %reg1027<def> = MOVRdRr %R12<kill>
Inspecting R12,inf = [0,6:0) 0 at 0*-(6) and %reg1027,0.000000e+00 = [6,54:0) 0 at 6-(54):
Joined. Result = R12,inf = [0,54:0) 0 at 0*-(54)
12 %reg1026<def> = MOVRdRr %R13<kill>
Inspecting R13,inf = [0,14:0) 0 at 0*-(14) and %reg1026,0.000000e+00 = [14,94:0)...
2010 Sep 04
3
[LLVMdev] Possible missed optimization?
On Sep 4, 2010, at 11:21 AM, Borja Ferrer wrote:
> I've noticed this pattern happening with other operators aswell, but used xor in this example. As i said before, i tried with different register allocation orders, but it will produce always the same result. GCC is emitting longer code, but since LLVM is so nearer to the optimal code sequence i wanted to reach it.
In LLVM, copies are