search for: movntp

...T) when >>> targeting 32-bit x86 machines which do not support mfence. What >>> instruction sequence should we be using instead? >>> >> >> Do they have non-temporal accesses in the ISA? >> > > I thought not but there appear to be instructions like movntps. mfence > was introduced in SSE2 while movntps and sfence were introduced in SSE. > So the new builtin could be sfence? I think the codegen you point out for SEQ_CST is fine if we fix the memory model as suggested. On Wed, Jan 13, 2016 at 10:59 AM, Tim Northover <t.p.northover at gmai...

...Comments are welcome, especially if there anyone else, that needs this >> kind of functionality or if people has already implemented something >> similar. > > Sure, this works. This is exactly the idea of the builtin functions in > GCC. For example, in SSE, the __builtin_ia32_movntps function does a > nontemporal store. > > To answer David's question, we already have direct support for this in > tblgen, for example, include/llvm/IntrinsicsX86.td contains: > > let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". &gt...

On Thu, Jan 14, 2016 at 1:10 PM, David Majnemer via llvm-dev < llvm-dev at lists.llvm.org> wrote: > > > On Wed, Jan 13, 2016 at 7:00 PM, Hans Boehm via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > >> I agree with Tim's assessment for ARM. That's interesting; I wasn't >> previously aware of that instruction. >> >> My

On Wed, 1 Aug 2007, [UTF-8] Mikael Lepist? wrote: >> def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, >> VR128:$src), >> "movntps {$src, $dst|$dst, $src}", >> [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>; >> >> There is corresponding code in llvm-gcc to tell GCC how to handle this >> built...

...ode level. > > Comments are welcome, especially if there anyone else, that needs this > kind of functionality or if people has already implemented something > similar. Sure, this works. This is exactly the idea of the builtin functions in GCC. For example, in SSE, the __builtin_ia32_movntps function does a nontemporal store. To answer David's question, we already have direct support for this in tblgen, for example, include/llvm/IntrinsicsX86.td contains: let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse_movnt_ps :...

Hi, I was talking with aKor in #llvm how we could implement custom operation support for our ASIP architecture. We came into solution that the best way would be to write new custom operation intrinsic and optimization pass for raising certain type of function calls to those intrinsics (similar to raising mallocs). Basically our custom operation are like calls, with operand name and multiple

Chris Lattner wrote: > On Wed, 1 Aug 2007, [UTF-8] Mikael Lepist? wrote: > >>> def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, >>> VR128:$src), >>> "movntps {$src, $dst|$dst, $src}", >>> [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>; >>> >>> There is corresponding code in llvm-gcc to tell GCC how to handle...

...machines which do not > support mfence. What instruction sequence should we > be using instead? > > > Do they have non-temporal accesses in the ISA? > > > I thought not but there appear to be instructions > like movntps. mfence was introduced in SSE2 while movntps and > sfence were introduced in SSE. > > > So the new builtin could be sfence? I think the codegen you point > out for SEQ_CST is fine if we fix the memory model as suggested. > > > I agree that it's fine to...

...define SET_SSE_PREFIX(dst, vex_pfx) do { \ + if ( vex_pfx ) \ + (dst) = sse_prefix[(vex_pfx) - 1]; \ +} while (0) + union vex { uint8_t raw[2]; struct { @@ -3850,6 +3860,76 @@ x86_emulate( case 0x19 ... 0x1f: /* nop (amd-defined) */ break; + case 0x2b: /* {,v}movntp{s,d} xmm,m128 */ + /* vmovntp{s,d} ymm,m256 */ + fail_if(ea.type != OP_MEM); + /* fall through */ + case 0x28: /* {,v}movap{s,d} xmm/m128,xmm */ + /* vmovap{s,d} ymm/m256,ymm */ + case 0x29: /* {,v}movap{s,d} xmm,xmm/m128 */ + /* vmovap{...