Displaying 9 results from an estimated 9 matches for "movlpd".
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2011 Nov 17
2
[LLVMdev] [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
Hello Hal,
> MultiSource/Applications/ClamAV - fails to compile shared_sha256.c with
> an error: error in backend: Cannot select: 0x4fbcb40: v2i64 =
> X86ISD::MOVLPD 0x4149e00, 0x418d930 [ID=596]
Please report this as a PR regardless of the pass. Bugs in the backend
should be fixed.
--
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University
2019 Nov 12
1
dovecot -2.2.24 on Fedora 31
...rogram: /usr/local/dovecot/libexec/dovecot/auth
[Thread debugging using libthread_db enabled]
Using host libthread_db library "/lib64/libthread_db.so.1".
Program received signal SIGSEGV, Segmentation fault.
__strcmp_ssse3 () at ../sysdeps/x86_64/multiarch/../strcmp.S:173
173 movlpd (%rdi), %xmm1
> Also doveconf -n could be useful.
Here it is:
# 2.2.36.4 (baf9232c1): /usr/local/dovecot/etc/dovecot/dovecot.conf
# OS: Linux 5.3.8-300.fc31.x86_64 x86_64 Fedora release 31 (Thirty One) ext3
# Hostname: seymour.fritz.box
auth_mechanisms = plain login
default_client_limit = 10...
2013 Jul 19
0
[LLVMdev] llvm.x86.sse2.sqrt.pd not using sqrtpd, calling a function that modifies ECX
...mm0
002E0108 xorpd xmm0,xmm0
002E010C movapd xmmword ptr [esp+0C0h],xmm0
002E0115 xorpd xmm1,xmm1
002E0119 xorpd xmm7,xmm7
002E011D movapd xmmword ptr [esp+0A0h],xmm1
002E0126 movapd xmmword ptr [esp+0B0h],xmm7
002E012F movapd xmm3,xmm1
002E0133 movlpd qword ptr [esp+0F0h],xmm3
002E013C movhpd qword ptr [esp+0E0h],xmm3
002E0145 movlpd qword ptr [esp+100h],xmm7
002E014E pshufd xmm0,xmm7,44h
002E0153 movdqa xmm5,xmm0
002E0157 xorpd xmm4,xmm4
002E015B mulpd xmm5,xmm4
002E015F pshufd xmm2,xmm3,4...
2011 Nov 30
0
[PATCH 2/4] x86/emulator: add emulation of SIMD FP moves
...("skipped\n");
+ printf("%-40s", "Testing movsd %xmm5,(%ecx)...");
+ memset(res, 0x77, 64);
+ memset(res + 10, 0x66, 8);
+ if ( stack_exec && cpu_has_sse2 )
+ {
+ extern const unsigned char movsd_to_mem[];
+
+ asm volatile ( "movlpd %0, %%xmm5\n\t"
+ "movhpd %0, %%xmm5\n"
+ ".pushsection .test, \"a\", @progbits\n"
+ "movsd_to_mem: movsd %%xmm5, (%1)\n"
+ ".popsection" :: "m" (...
2013 Jul 19
4
[LLVMdev] SIMD instructions and memory alignment on X86
Hmm, I'm not able to get those .ll files to compile if I disable SSE and I
end up with SSE instructions(including sqrtpd) if I don't disable it.
On Thu, Jul 18, 2013 at 10:53 PM, Peter Newman <peter at uformia.com> wrote:
> Is there something specifically required to enable SSE? If it's not
> detected as available (based from the target triple?) then I don't think
2019 Nov 12
2
dovecot -2.2.24 on Fedora 31
On Tue, 12 Nov 2019 00:17:28 +0100 Frank Elsner via dovecot wrote:
> On Mon, 11 Nov 2019 23:47:27 +0100 Frank Elsner via dovecot wrote:
[ ... ]
> I narrowed the probelem down to the warnings
>
> Warning: service auth { client_limit=128 } is lower than required under max. load (768)
> Warning: service anvil { client_limit=256 } is lower than required under max. load (643)
These
2011 Nov 16
0
[LLVMdev] [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
...violations,
etc., and at least on x86_64, all test cases pass except for a few; and
all of these failures look like instruction-selection bugs. For example:
MultiSource/Applications/ClamAV - fails to compile shared_sha256.c with
an error: error in backend: Cannot select: 0x4fbcb40: v2i64 =
X86ISD::MOVLPD 0x4149e00, 0x418d930 [ID=596]
SingleSource/Benchmarks/BenchmarkGame/n-body - crashes; incorrectly
generates an aligned vector load for an unaligned load (so passing
-bb-vectorize-aligned-only will make it work for now)
-Hal
On Tue, 2011-11-15 at 17:38 -0600, Hal Finkel wrote:
> Tobias,
>...
2011 Nov 15
3
[LLVMdev] [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
Tobias,
I've attached the latest version of my autovectorization patch. I was
able to add support for using the ScalarEvolution analysis for
load/store pairing (thanks for your help!). This led to a modest
performance increase and a modest compile-time increase. This version
also has a cutoff as you suggested (although the default value is set
high (4000 instructions between pairs) because
2013 Oct 15
0
[LLVMdev] [llvm-commits] r192750 - Enable MI Sched for x86.
...7 2013
>> @@ -1,8 +1,8 @@
>> ; RUN: llc -march=x86 -mcpu=generic -mattr=+sse4.2 < %s | FileCheck %s
>> ; RUN: llc -march=x86 -mcpu=atom < %s | FileCheck -check-prefix=ATOM %s
>>
>> -; CHECK: paddd
>> ; CHECK: movl
>> +; CHECK: paddd
>> ; CHECK: movlpd
>>
>> ; Scheduler causes produce a different instruction order
>>
>> Modified: llvm/trunk/test/CodeGen/X86/win64_alloca_dynalloca.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/win64_alloca_dynalloca.ll?rev=192750&r1=192749&r2=1927...