search for: movimmshf32

Displaying 4 results from an estimated 4 matches for "movimmshf32".

2016 Aug 22
3
Instruction itineraries and fence/barrier instructions
...ed was: xstg_intrinsic: # @xstg_intrinsic # BB#0: # %entry subI r509, r509, 16, 64 store r510, r509, 0, 64 bitop1 r510, r509, 0, OR, 64 store r0, r510, 12, 32 movimm r1, %hi(write_me), 64 movimmshf32 r1, r1, %lo(write_me) store r0, r1, 0, 32 fence 2 movimm r0, %hi(read_me), 64 movimmshf32 r0, r0, %lo(read_me) load r1, r0, 0, 32 bitop1 r509, r510, 0, OR, 64 load r510, r509, 0, 64 addI r509, r509, 16, 64 jabs r...
2016 Aug 22
2
Instruction itineraries and fence/barrier instructions
...; > # BB#0: # %entry > > subI r509, r509, 16, 64 > > store r510, r509, 0, 64 > > bitop1 r510, r509, 0, OR, 64 > > store r0, r510, 12, 32 > > movimm r1, %hi(write_me), 64 > > movimmshf32 r1, r1, %lo(write_me) > > store r0, r1, 0, 32 > > fence 2 > > movimm r0, %hi(read_me), 64 > > movimmshf32 r0, r0, %lo(read_me) > > load r1, r0, 0, 32 > > bitop1 r509, r510, 0, OR, 64 > > load...
2016 Jan 07
2
TableGen error message: top-level forms in instruction pattern should have void types
...mbly code: .Ltmp0: .cfi_def_cfa_offset 48 store r510, r509, 0, 64 .Ltmp1: .cfi_offset 510, -48 bitop1 r510, r509, 0, OR, 64 .Ltmp2: .cfi_def_cfa_register 510 store r0, r510, 44, 32 store r1, r510, 32, 64 movimm r0, %hi(xint), 64 movimmshf32 r0, r0, %lo(xint) movimm r1, %rel(answer), 64 #<--- relevant lines load r1, r1, 0, 32 #<--- ... (%rel is a macro that returns the delta from the global section to the 'answer' symbol) Instead of that last load instruction there, I want i...
2016 Jan 07
2
TableGen error message: top-level forms in instruction pattern should have void types
On Thu, Jan 7, 2016 at 12:21 PM, Krzysztof Parzyszek via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On 1/7/2016 1:55 PM, Phil Tomson via llvm-dev wrote: > >> >> let Uses= [GRP] in { >> def RelAddr : XSTGPseudo< (outs), >> (ins GPRC:$spoff, GPRC:$dst), >>