Displaying 3 results from an estimated 3 matches for "movi32rr".
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mov32rr
2010 Jul 28
3
[LLVMdev] Subregister coalescing
...D4[<unknown>]
76 %reg16393<def> = LDWr %reg16386<kill>, 0; mem:LD4[<unknown>]
84 %reg16394<def> = LDWr %reg16387<kill>, 0; mem:LD4[<unknown>]
92 %reg16395<def> = LDWr %reg16388<kill>, 0; mem:LD4[<unknown>]
132 %reg16400:1<def,dead> = MOVI32rr %reg16392<kill>
140 %reg16400:2<def> = MOVI32rr %reg16393<kill>
148 %reg16400:3<def> = MOVI32rr %reg16394<kill>
156 %reg16400:4<def> = MOVI32rr %reg16395<kill>
but then Live Range Analysis asserts because of multiply defined %
reg16400.
Can anyone give me...
2010 Jul 28
0
[LLVMdev] Subregister coalescing
...> 76 %reg16393<def> = LDWr %reg16386<kill>, 0; mem:LD4[<unknown>]
> 84 %reg16394<def> = LDWr %reg16387<kill>, 0; mem:LD4[<unknown>]
> 92 %reg16395<def> = LDWr %reg16388<kill>, 0; mem:LD4[<unknown>]
> 132 %reg16400:1<def,dead> = MOVI32rr %reg16392<kill>
> 140 %reg16400:2<def> = MOVI32rr %reg16393<kill>
> 148 %reg16400:3<def> = MOVI32rr %reg16394<kill>
> 156 %reg16400:4<def> = MOVI32rr %reg16395<kill>
>
> but then Live Range Analysis asserts because of multiply defined %
>...
2017 Mar 22
3
REG_SEQUENCE use question
...another, I'm
trying to use the following pattern:
def LoReg: OutPatFrag<(ops node:$Rd), (EXTRACT_SUBREG (i64 $Rd), isub_lo)>;
def HiReg: OutPatFrag<(ops node:$Rd), (EXTRACT_SUBREG (i64 $Rd), isub_hi)>;
def MOVi64rr : Pat<(set GPR64:$Rd, GPR64:$Rn),
(REG_SEQUENCE GPR64,
(MOVi32rr (HiReg GPR64:$Rn)),
isub_hi,
(MOVi32rr (LoReg GPR64:$Rn)),
isub_lo)>;
isub_hi and isub_lo are subregs of a single 64-bit virtual reg.
When trying to compile it, im getting the following error:
MOVi64rr: (set GPR64:i64:$Rd, GPR64:i64:$Rn)
MOVi64rr: (REG_SEQUENCE:<empt...