search for: movgg

...or outputs). So a solution that may work for you would be to define permutations of the instructions that explicitly specify what type of operands your instruction takes (because different instructions need different LLVM opcodes) but the instructions would print out the same, so in your example: MOVgg : General, General MOVwg : Write-only, General MOVwr : Write-only, Read-only Note that if they all have the same "mov $dest, $src" print string, they will be printed out identically, but you need to separate them anyway. If you look at the X86 backend, you might find many flavors of MOV...

Hi, everyone. I' have three set of registers - read-only regs, general purpose regs (read and write), and write-only regs. How should I partition them into different RegisterClasses so that I can easy define the instruction? All RegisterClasses must be mutally exclusive. That is, a register can only be in a RegisterClass. Otherwise TableGen will raise an error message. def

...all 'RegisterClass'es to be 'packed' (first argument of RegisterClass): def GeneralPurposeRC : RegisterClass<packed, 128, [R0, R1]>; def INT_ReadOnlyRC : RegisterClass<packed, 128, [I0, I1]>; def FP_ReadOnlyRC : RegisterClass<packed, 128, [F0, F1]>; def MOVgg : BinaryInst<0x51, ( ops GeneralPurposeRC :$dest, ope GeneralPurposeRC :$src), "mov $dest, $src">; def MOVgi : BinaryInst<0x52, ( ops GeneralPurposeRC :$dest, ope INT_ReadOnlyRC :$src), "mov $dest, $src">; def MOVgf : BinaryInst<0x52, ( o...

...ld be to define permutations of >> the instructions that explicitly specify what type of operands your >> instruction takes (because different instructions need different LLVM >> opcodes) but the instructions would print out the same, so in your >> example: >> >> MOVgg : General, General >> MOVwg : Write-only, General >> MOVwr : Write-only, Read-only >> >> Note that if they all have the same "mov $dest, $src" print string, they >> will be printed out identically, but you need to separate them anyway. >> If you look at...