Displaying 6 results from an estimated 6 matches for "movg".
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2009 Apr 16
0
[LLVMdev] Using CallingConvLower in ARM target
Greetings Sandeep
I have tested crosscompiling llvm2.6 svn trunk 69279 + your patch for
armv7a hardware.
I wanted to see if it would build and if any unexpected failing tests in
the testsuite would start to work using your patch.
It built fine and your attached tests in the patch runs fine for me :)
Now something fun this Generic test now works that previously failed:
$ llvm-as <
2013 Jan 23
2
[LLVMdev] introducing sign extending halfword loads into the LLVM IR
...# mask with 0xffff to convert to short again
> lsl r4, r4, #16 # this lsl and the following
> asr r5, r4, #16 # asr implement sign-extension to 32 bits again ....
> ldr r4, .LCPI1_1
> cmn r5, #2048
> movge r4, r3
> .LBB1_3:
> str r4, [r2, r0, lsl #2]
> add r0, r0, #1
> add r1, r1, #2
> cmp r0, #67
> blt .LBB1_1
>
> Clearly the sign-extensions are not handled correctly ...
2009 Apr 08
4
[LLVMdev] What is the state of LLVM's ARM backend
Hello Evan and Robert
I have been investigating the unexpected test failures from the ARM
nightly builders in order to get a better picture why the ARM backend
don't pass the whole testsuite: I have run the failing tests manually on
my arm board and can now categorize most of the thirteen unexpected
CodeGen failures in four categories:
1. llvm don't lower MVT::i64 properly on arm
2013 Jan 24
0
[LLVMdev] introducing sign extending halfword loads into the LLVM IR
...ffff to convert to short again
>> lsl r4, r4, #16 # this lsl and the following
>> asr r5, r4, #16 # asr implement sign-extension to 32 bits again ....
>> ldr r4, .LCPI1_1
>> cmn r5, #2048
>> movge r4, r3
>> .LBB1_3:
>> str r4, [r2, r0, lsl #2]
>> add r0, r0, #1
>> add r1, r1, #2
>> cmp r0, #67
>> blt .LBB1_1
>>
>> Clearly the sign-extensions are not handled correctly ...
2009 Apr 16
2
[LLVMdev] Using CallingConvLower in ARM target
After wasting an inordinate amount of time trying to get test-suite to
run on arm-apple-darwin so I could reproduce your results, attached is
a patch that fixes the small copy&paste error of having 8-byte
alignment for stack-allocated f64s instead of the proper 4-byte. I've
updated the patch to the top of trunk changes as well.
deep
On Fri, Feb 27, 2009 at 8:31 PM, Sandeep Patel
2013 Jan 21
3
[LLVMdev] introducing sign extending halfword loads into the LLVM IR
On Jan 21, 2013, at 6:34 AM, Justin Holewinski <justin.holewinski at gmail.com> wrote:
>
> On Mon, Jan 21, 2013 at 9:16 AM, Bjorn De Sutter <bjorn.desutter at elis.ugent.be> wrote:
> On 21 Jan 2013, at 14:39, Justin Holewinski <justin.holewinski at gmail.com> wrote:
>
>> Instruction selection happens on a different IR: SelectionDAG. In this IR, there are