Displaying 8 results from an estimated 8 matches for "mov8rr".
2007 Jun 27
0
[LLVMdev] Live Intervals Question
On Tuesday 26 June 2007 14:57, David Greene wrote:
> > EAX and its sub-registers are defined by the MOV8rr instruction
> >
> > implicitly:
> > > 28 %AL<dead> = MOV8rr %reg1024<kill>, %EAX<imp-def>
> > > MOV8rr %mreg(2)<d> %reg1024 %mreg(17)<d>
> >
> > So their live ranges start at 28+2.
>
> Yep, this makes sense to me. But AL...
2007 Jun 26
4
[LLVMdev] Live Intervals Question
Evan, thanks for responding so quickly.
On Tuesday 26 June 2007 14:11, Evan Cheng wrote:
> On Jun 26, 2007, at 11:20 AM, David A. Greene wrote:
> > 28 %AL<dead> = MOV8rr %reg1024<kill>, %EAX<imp-def>
> > MOV8rr %mreg(2)<d> %reg1024 %mreg(17)<d>
> > 32 CALL64pcrel32 <ga:printf>, %RDI<kill>, %RAX<imp-def>, %RCX<imp-
> > def,dead>,
> > %RDX<imp-def,dead>, %RSI<imp-def,dead>, %RDI<im...
2007 Jun 26
0
[LLVMdev] Live Intervals Question
On Jun 26, 2007, at 11:20 AM, David A. Greene wrote:
>
> 28 %AL<dead> = MOV8rr %reg1024<kill>, %EAX<imp-def>
> MOV8rr %mreg(2)<d> %reg1024 %mreg(17)<d>
> 32 CALL64pcrel32 <ga:printf>, %RDI<kill>, %RAX<imp-def>, %RCX<imp-
> def,dead>,
> %RDX<imp-def,dead>, %RSI<imp-def,dead>, %RDI<imp-def,dead>,
>...
2007 Jun 26
3
[LLVMdev] Live Intervals Question
...MOV8r0 %reg1024<d>
20 %reg1025 = LEA64r %NOREG, 1, %NOREG,
<ga:initialized$$$CFE_id_cc092431_main>
LEA64r %reg1025<d> %mreg(0) 1 %mreg(0) <ga:initialized$$$CFE_id_cc092431_main>
24 %RDI = MOV64rr %reg1025<kill>
MOV64rr %mreg(78)<d> %reg1025
28 %AL<dead> = MOV8rr %reg1024<kill>, %EAX<imp-def>
MOV8rr %mreg(2)<d> %reg1024 %mreg(17)<d>
32 CALL64pcrel32 <ga:printf>, %RDI<kill>, %RAX<imp-def>, %RCX<imp-def,dead>,
%RDX<imp-def,dead>, %RSI<imp-def,dead>, %RDI<imp-def,dead>,
%R8<imp-def,dead>...
2007 Jun 27
0
[LLVMdev] Live Intervals Question
On Jun 26, 2007, at 12:57 PM, David Greene wrote:
> Evan, thanks for responding so quickly.
>
> On Tuesday 26 June 2007 14:11, Evan Cheng wrote:
>> On Jun 26, 2007, at 11:20 AM, David A. Greene wrote:
>>> 28 %AL<dead> = MOV8rr %reg1024<kill>, %EAX<imp-def>
>>> MOV8rr %mreg(2)<d> %reg1024 %mreg(17)<d>
>>> 32 CALL64pcrel32 <ga:printf>, %RDI<kill>, %RAX<imp-def>, %RCX<imp-
>>> def,dead>,
>>> %RDX<imp-def,dead>, %RSI<imp-def,dead>...
2008 Sep 03
2
[LLVMdev] Codegen/Register allocation question.
...0, <ga:.str1>
52 %RDI<def> = MOV64rr %reg1028<kill>
60 %XMM0<def> = FsMOVAPDrr %reg1027
68 %XMM1<def> = FsMOVAPDrr %reg1027
76 %XMM2<def> = FsMOVAPDrr %reg1027
84 %XMM3<def> = FsMOVAPDrr %reg1027<kill>
92 %AL<def> = MOV8rr %reg1026<kill>
100 CALL64pcrel32 <ga:printf>, %RDI<kill>, %XMM0<kill>,
%XMM1<kill>, %XMM2<kill>, %XMM3<kill>, %AL<kill>, %RAX<imp-def>,
%RCX<imp-def,dead>, %RDX<imp-def,dead>, %RSI<imp-def,dead>,
%RDI<imp-def,dead>, %...
2008 Sep 04
0
[LLVMdev] Codegen/Register allocation question.
...%RDI<def> = MOV64rr %reg1028<kill>
> 60 %XMM0<def> = FsMOVAPDrr %reg1027
> 68 %XMM1<def> = FsMOVAPDrr %reg1027
> 76 %XMM2<def> = FsMOVAPDrr %reg1027
> 84 %XMM3<def> = FsMOVAPDrr %reg1027<kill>
> 92 %AL<def> = MOV8rr %reg1026<kill>
> 100 CALL64pcrel32 <ga:printf>, %RDI<kill>, %XMM0<kill>,
> %XMM1<kill>, %XMM2<kill>, %XMM3<kill>, %AL<kill>, %RAX<imp-def>,
> %RCX<imp-def,dead>, %RDX<imp-def,dead>, %RSI<imp-def,dead>,
> %RDI<...
2010 May 18
2
[LLVMdev] Fast register allocation
...def>, %EFLAGS<imp-def>, %RSP<imp-use>
%reg1030<def> = LEA64r %RIP, 1, %reg0, <ga:@.str>
%reg1031<def> = MOV8r0 %EFLAGS<imp-def,dead>
%RDI<def> = MOV64rr %reg1030
%ESI<def> = MOV32rr %reg1028
%EDX<def> = MOV32rr %reg1029
%AL<def> = MOV8rr %reg1031
CALL64pcrel32 <ga:@printf>, %RDI, %ESI, %EDX, %AL, %RAX<imp-def>, %RDX<imp-def>, %RSI<imp-def>, %RDI<imp-def>, %RSP<imp-use>, ...
When finding a register for %reg1028, RAFast sees that it is later copied to %ESI. It is allocated %ESI and the copy disap...