Displaying 2 results from an estimated 2 matches for "mov64topqirr".
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mov64topqirm
2012 Jul 26
1
[LLVMdev] Question about ExpandPostRAPseudos.cpp
...ize-regalloc=0 -verify-machineinstrs -mcpu-atom", the test fails right after the Post-RA pseudo instruction pass with the messages
*** Bad machine code: Using an undefined physical register ***
- function: autogen_SD24657
- basic block: BB 0x2662d60 (BB#0)
- instruction: %XMM0<def> = MOV64toPQIrr %RAX<kill>
- operand 1: %RAX<kill>
LLVM ERROR: Found 1 machine code errors.
This happens because, on entry to the pass, we have
%RAX<def> = SUBREG_TO_REG 0, %R9D, 4
%XMM0<def> = MOV64toPQIrr %RAX<kill>
The pass converts (around about line 132 in Exp...
2007 Dec 12
2
[LLVMdev] Bogus X86-64 Patterns
...===============================
--- /usr/people/djg/svn/test/official.llvm/llvm/lib/Target/X86/X86InstrX86-64.td
(revision 32608)
+++ /usr/people/djg/svn/test/official.llvm/llvm/lib/Target/X86/X86InstrX86-64.td
(revision 32609)
@@ -1110,33 +1110,33 @@
// Move instructions...
def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (ops VR128:$dst, GR64:$src),
- "movq {$src, $dst|$dst, $src}",
+ "mov{d|q} {$src, $dst|$dst, $src}",
[(set VR128:$dst,
(v2i64 (scalar_to_vector GR64:$src)...