search for: mov64ri64i32

...81 The workaround I found is to add this : Index: lib/Target/X86/X86Instr64bit.td =================================================================== --- lib/Target/X86/X86Instr64bit.td (revision 105882) +++ lib/Target/X86/X86Instr64bit.td (working copy) @@ -1832,6 +1832,8 @@ (MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>; def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)), (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>; +def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)), + (MOV64ri32 tglobaltlsaddr :$dst)>, Requires&l...

...dd this : > > Index: lib/Target/X86/X86Instr64bit.td > =================================================================== > --- lib/Target/X86/X86Instr64bit.td (revision 105882) > +++ lib/Target/X86/X86Instr64bit.td (working copy) > @@ -1832,6 +1832,8 @@ > (MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>; > def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)), > (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>; > +def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)), > + (MOV64ri32 tglobaltlsaddr :$ds...

...Index: lib/Target/X86/X86Instr64bit.td >> =================================================================== >> --- lib/Target/X86/X86Instr64bit.td (revision 105882) >> +++ lib/Target/X86/X86Instr64bit.td (working copy) >> @@ -1832,6 +1832,8 @@ >> (MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>; >> def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)), >> (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>; >> +def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)), >> + (MOV64ri32 t...

...els free to clobber RDX when it should be set up for the call? I tried running the final IR->x86 lowering with -print-after-all, and it appears all is well after 'Two-Address instruction pass': MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 1; mem:ST4[%val] %vreg3<def> = MOV64ri64i32 4; GR64:%vreg3 %R8<def> = COPY %vreg3; GR64:%vreg3 INLINEASM <es:> [sideeffect] [attdialect], $0:[reguse], %R8 %vreg4<def> = LEA64r <fi#0>, 1, %noreg, 0, %noreg; GR64:%vreg4 %R10<def> = COPY %vreg4; GR64:%vreg4 INLINEASM <es:> [sideeffect...

...nstr64bit.td >>> =================================================================== >>> --- lib/Target/X86/X86Instr64bit.td (revision 105882) >>> +++ lib/Target/X86/X86Instr64bit.td (working copy) >>> @@ -1832,6 +1832,8 @@ >>> (MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>; >>> def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)), >>> (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>; >>> +def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)), >>> +...

...EI::insertPrologEpilogCode: === >> before emitEpilogue - insn: PUSH64r %RBP<kill>, %RSP<imp-def>, %RSP<imp-use> - insn: PROLOG_LABEL <MCSym=.Ltmp2> - insn: %RBP<def> = MOV64rr %RSP - insn: PROLOG_LABEL <MCSym=.Ltmp3> - insn: %RDI<def> = MOV64ri64i32 60910096 - insn: %RAX<def> = MOV64ri <ga:@_ZN010HelloWorld4mainEPN13ContainerSVecE> - insn: TCRETURNri64 %RAX<kill>, 0, %RDI<kill>, %RAX<imp-def,dead>, %RDI<imp-def,dead>, %RSP<imp-use>, ... - insn: RET * PEI::insertPrologEpilogCode: === <<...

On Aug 26, 2010, at 12:59 PMPDT, Eric Christopher wrote: > On Aug 26, 2010, at 12:25 PM, Yuri wrote: >> On 08/26/2010 11:53, Eric Christopher wrote: >>> Could you get it to print out the instruction when it happens? >>> (just change the line above the error message to print it out to >>> errs()). >>> >>> It basically means that a pseudo

...rrectly) identified at rematable (for the SUB64rr): ##### spilling(a): %reg1591,3.3557 = [2178,2802:4)[2802,2810:3)[2810,2818:2) [2818,2966:1)[2966,7840:0) 0 at 2966 1 at 2818-(2966) 2 at 2810-(2818) 3 at 2802-(2810) 4 at 2178-(2802) Set %reg2559 rematerialized with def: %reg1591<def> = MOV64ri64i32 32 ; srcLine 0 Assigned remat id 262151 to %reg2559 +[2180,2182:0) Added new interval: %reg2559,0 = [2180,2182:0) 0 at 2180 +[2182,2526:0) Added interval split reuse: %reg2559,1000 = [2180,2526:0) 0 at 2180 +[2526,2802:0) +[2802,2803:1) Added interval split reuse: %reg2559,2000 =...

...gEpilogCode: === >> before emitEpilogue > - insn: PUSH64r %RBP<kill>, %RSP<imp-def>, %RSP<imp-use> > - insn: PROLOG_LABEL <MCSym=.Ltmp2> > - insn: %RBP<def> = MOV64rr %RSP > - insn: PROLOG_LABEL <MCSym=.Ltmp3> > - insn: %RDI<def> = MOV64ri64i32 60910096 > - insn: %RAX<def> = MOV64ri > <ga:@_ZN010HelloWorld4mainEPN13ContainerSVecE> > - insn: TCRETURNri64 %RAX<kill>, 0, %RDI<kill>, %RAX<imp-def,dead>, > %RDI<imp-def,dead>, %RSP<imp-use>, ... > - insn: RET > * PEI::insertProl...

...= >> before emitEpilogue >> - insn: PUSH64r %RBP<kill>, %RSP<imp-def>, %RSP<imp-use> >> - insn: PROLOG_LABEL <MCSym=.Ltmp2> >> - insn: %RBP<def> = MOV64rr %RSP >> - insn: PROLOG_LABEL <MCSym=.Ltmp3> >> - insn: %RDI<def> = MOV64ri64i32 60910096 >> - insn: %RAX<def> = MOV64ri <ga:@_ZN010HelloWorld4mainEPN13ContainerSVecE> >> - insn: TCRETURNri64 %RAX<kill>, 0, %RDI<kill>, %RAX<imp-def,dead>, %RDI<imp-def,dead>, %RSP<imp-use>, ... >> - insn: RET >> * PEI::insertProlo...

...itEpilogue >>> - insn: PUSH64r %RBP<kill>, %RSP<imp-def>, %RSP<imp-use> >>> - insn: PROLOG_LABEL <MCSym=.Ltmp2> >>> - insn: %RBP<def> = MOV64rr %RSP >>> - insn: PROLOG_LABEL <MCSym=.Ltmp3> >>> - insn: %RDI<def> = MOV64ri64i32 60910096 >>> - insn: %RAX<def> = MOV64ri >>> <ga:@_ZN010HelloWorld4mainEPN13ContainerSVecE> >>> - insn: TCRETURNri64 %RAX<kill>, 0, %RDI<kill>, %RAX<imp- >>> def,dead>, %RDI<imp-def,dead>, %RSP<imp-use>, ... >>&g...