search for: mov64mr

...ansforms 0B BB#0: derived from LLVM BB %entry 16B %vreg0<def> = MOV64rm %RIP, 1, %noreg, <ga:@val>[TF=5], %noreg; mem:LD8[GOT] GR64:%vreg0 32B %vreg1<def> = MOV64rm %RIP, 1, %noreg, <ga:@p>[TF=5], %noreg; mem:LD8[GOT] GR64:%vreg1 48B MOV64mr %vreg1, 1, %noreg, 0, %noreg, %vreg0; mem:ST8[@p](tbaa=!"any pointer") GR64:%vreg1,%vreg0 64B %vreg2<def> = MOV64ri 12345123400; GR64:%vreg2 80B MOV64mr %vreg0, 1, %noreg, 0, %noreg, %vreg2; mem:ST8[@val](tbaa=!"long long") GR64:%vreg0,%vreg2 96B...

For the little C test program where a constant is stored in memory and also used as a parameter: #include <stdint.h> uint64_t val, *p; extern uint64_t xtr( uint64_t); uint64_t caller() { uint64_t x; p = &val; x = 12345123400L; *p = x; return xtr(x); } clang (3.2, 3.3 and svn) generates the following X86 code (at -O3): caller: movq

...erived from LLVM BB %entry > 16B %vreg0<def> = MOV64rm %RIP, 1, %noreg, > <ga:@val>[TF=5], %noreg; mem:LD8[GOT] GR64:%vreg0 > 32B %vreg1<def> = MOV64rm %RIP, 1, %noreg, <ga:@p>[TF=5], > %noreg; mem:LD8[GOT] GR64:%vreg1 > 48B MOV64mr %vreg1, 1, %noreg, 0, %noreg, %vreg0; > mem:ST8[@p](tbaa=!"any pointer") GR64:%vreg1,%vreg0 > 64B %vreg2<def> = MOV64ri 12345123400; GR64:%vreg2 > 80B MOV64mr %vreg0, 1, %noreg, 0, %noreg, %vreg2; > mem:ST8[@val](tbaa=!"long long") GR64:...

Hi all, I met a new problem in the process of my project. I have got an address by mmap. And I want to build a MachineInstr of MOV64mr to move a value to the address. But it seems that the MachinePointerInfo needs a pointer to a Value. So can I create a MachineMemOperand directly with the address (is a long*) ? Or I need to try some other methods? Thanks a lot, Will -------------- next part -------------- An HTML attachment was sc...

Usually I will search the target directory, X86 in your case, to see how MOV64mr is used with BuildMI to generate the instruction I want. 2018-04-16 16:25 GMT+08:00 Will Lester via llvm-dev <llvm-dev at lists.llvm.org>: > Hi all, > I met a new problem in the process of my project. > I have got an address by mmap. And I want to build a MachineInstr of MOV64mr &gt...

...ing intervals for spills for interval: %reg2613,5.56561 = [2714,2718:0) [2718,2726:1)[2726,2766:2)[2766,2926:3)[2926,2934:4)[2934,2935:5) 0 at 2714 1 at 2718 2 at 2726 3 at 2766 4 at 2926 5 at 2934 Mapped %reg2613 and folded instruction: %reg2613<def> = MOV64rr %reg1607 ; srcLine 0 into: MOV64mr <fi#184>, 1, %reg0, 0, %reg1607 ; srcLine 0 Virt folded mapped NewMI 0x9883480: MOV64mr <fi#184>, 1, %reg0, 0, %reg1607 ; srcLine 0 to %reg2613 Mapped %reg2613 and folded instruction: %reg2613<def> = SUB64rr %reg2613, %reg1577<kill>, %EFLAGS<imp-def,dead> ; srcLi...

...y > > 16B %vreg0<def> = MOV64rm %RIP, 1, %noreg, > > <ga:@val>[TF=5], %noreg; mem:LD8[GOT] GR64:%vreg0 > > 32B %vreg1<def> = MOV64rm %RIP, 1, %noreg, <ga:@p>[TF=5], > > %noreg; mem:LD8[GOT] GR64:%vreg1 > > 48B MOV64mr %vreg1, 1, %noreg, 0, %noreg, %vreg0; > > mem:ST8[@p](tbaa=!"any pointer") GR64:%vreg1,%vreg0 > > 64B %vreg2<def> = MOV64ri 12345123400; GR64:%vreg2 > > 80B MOV64mr %vreg0, 1, %noreg, 0, %noreg, %vreg2; > > mem:ST8[@val](tbaa=!"lo...

...y to bother you again. Since I have met the problem, how to check used registers and avoid clobbering live registers, which you mentioned in the email. I am working in the function X86InstrInfo::storeRegToStackSlot, which is in lib/Target/X86/X86InstrInfo.cpp. And I have an extra problem, may I use MOV64mr and two addReg to set two registers as its arguments? I want to use content of one register as the address to be stored, and content of the other register as the source. Thanks a lot! Will 2018-04-13 22:11 GMT+08:00 Will Lester <hslester96 at gmail.com>: > Thanks for your help! I'm...

Thanks for your help! I'm much more clear about this problem. Will 2018-04-13 17:53 GMT+08:00 Tim Northover <t.p.northover at gmail.com>: > Hi Will, > > On 13 April 2018 at 09:50, Will Lester via llvm-dev > <llvm-dev at lists.llvm.org> wrote: > > I have used BuildMI to build a MachineInstr. But it seems that a call > > MachineInstr only has one parameter

...re. May I do not create a MachineMemOperand, just store the address in a register, and use some MachineInstr to store the value to the address? 2018-04-16 21:19 GMT+08:00 陳韋任 <chenwj.cs97g at g2.nctu.edu.tw>: > Usually I will search the target directory, X86 in your case, to see > how MOV64mr is used with BuildMI to generate the instruction I want. > > 2018-04-16 16:25 GMT+08:00 Will Lester via llvm-dev < > llvm-dev at lists.llvm.org>: > > Hi all, > > I met a new problem in the process of my project. > > I have got an address by mmap. And I want to build...

...= 0; + + for (MCPhysReg Reg : GPRs) { + if (++RI > arg_size) + break; + + SaveSize += SlotSize; + +#if 1 + BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64r)) + .addReg(Reg) + .setMIFlag(MachineInstr::FrameSetup); +#else + // MOV64mr Reg, -SaveSize(%rbp) + addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64mr)), + FramePtr, true, -SaveSize) + .addReg(Reg) + .setMIFlag(MachineInstr::FrameSetup); +#endif + } + + StackSize += SaveSize; + MFI.setStackSize(StackSize);...

...et %rbp, -16 movq %rsp, %rbp ## <MCInst #1491 MOV64rr ## <MCOperand Reg:106> ## <MCOperand Reg:114>> Ltmp4: .cfi_def_cfa_register %rbp movq %rdi, -8(%rbp) ## <MCInst #1482 MOV64mr ## <MCOperand Reg:106> ## <MCOperand Imm:1> ## <MCOperand Reg:0> ## <MCOperand Imm:-8>...

Hi, In GCC there is one useful option -dp (or -dP for more verbose output) to annotate assembler with instruction patterns, that was used when assembler was generated. For example: double test(long long s) { return s; } gcc -S -dp -O0 test.c test: .LFB0: .cfi_startproc pushq %rbp # 18 *pushdi2_rex64/1 [length = 1] .cfi_def_cfa_offset 16 movq %rsp, %rbp # 19 *movdi_1_rex64/2

...<MCOperand Imm:1> > # <MCOperand Reg:0> > # <MCOperand Imm:0> > # <MCOperand Reg:0>> > movq %r15, %gs:(%r14) # <MCInst #1803 MOV64mr > # <MCOperand Reg:117> > # <MCOperand Imm:1> > # <MCOperand Reg:0> > # <MCOperand Imm:0> >...

...TACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def>, %RSP<imp-use> MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[FixedStack6] JMP_4 <BB#3> entry BB#0 MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0 MOV32mr <fi#1>, 1, %noreg, 0, %noreg, %EDI<kill> MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %RSI<kill> MOV32mi <fi#3>, 1, %noreg, 0, %noreg, 0 MOV32mi <fi#4>, 1, %noreg, 0, %noreg, 4 %EDI<def> = MOV32rm <fi#3>, 1, %noreg, 0, %noreg %EDI<def,tied1> = SUB32rm %EDI<tied0>, <fi#4>, 1, %noreg, 0, %noreg, %EFLAG...

The size suffix thing is a weird quirk in our assembler I should look into fixing. Instructions in at&t syntax usually have a size suffix that is often optional For example: add %ax, %bx and addw %ax, %bx Are equivalent because the register name indicates the size. but for an instruction like this addw $1, (%ax) There is nothing to infer the size from so an explicit suffix is

...     ## <MCInst #1491 MOV64rr >                                        ##  <MCOperand Reg:106> >                                        ##  <MCOperand Reg:114>> > Ltmp4: >        .cfi_def_cfa_register %rbp >        movq    %rdi, -8(%rbp)          ## <MCInst #1482 MOV64mr >                                        ##  <MCOperand Reg:106> >                                        ##  <MCOperand Imm:1> >                                        ##  <MCOperand Reg:0> >                                        ##  <MCOperand Imm:-8> >    ...

On Tue, 18 Dec 2018 at 07:11, Gleb Popov via llvm-dev <llvm-dev at lists.llvm.org> wrote: > However, I haven't managed to get a "Constant<>" in the DAG when compiling for X86. I'm interested in how it is lowered. Can you please give me some guidance on this? How are you looking? When I run "llc -mtriple=x86_64-linux-gnu -debug-only=isel" on your IR I get

...reg3<def> = COPY %vreg2<kill>; GR64:%vreg3,%vreg2 %vreg5<def> = MOV64ri <ga:@.str>; GR64:%vreg5 MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval] MOV32mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST4[%argc.addr] GR32:%vreg1 MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%argv.addr] GR64:%vreg3 ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def>, %RSP<imp-use> %RDI<def> = COPY %vreg5; GR64:%vreg5 %AL<def> = MOV8ri 0 CALL64pcrel32 <ga:@printf>, &...

...INLINEASM <es:> [sideeffect] [attdialect], $0:[reguse], %RDI<kill> INLINEASM <es:> [sideeffect] [attdialect], $0:[regdef], %RDI<imp-def> %RAX<def> = MOV64ri64i32 54 INLINEASM <es:> [sideeffect] [attdialect], $0:[regdef], %RSI<imp-def> MOV64mr %RSP, 1, %noreg, -16, %noreg, %RDX<kill>; mem:ST8[FixedStack1] INLINEASM <es:> [sideeffect] [attdialect], $0:[regdef], %RDX<imp-def> INLINEASM <es:> [sideeffect] [attdialect], $0:[regdef], %R10<imp-def> INLINEASM <es:> [sideeffect] [attdialect], $0...