search for: mov32to32_

...>> register class per machine value type. > > The x86 backend has an example of a partial solution. The GR32 > register class has a subset, GR32_, which is the registers in GR32 > that support 8-bit subregs. Instructions that reference 8-bit subregs > are emitted with a copy (MOV32to32_) to put the value in a virtual > register of the needed class. This copy may then optimized away > by subsequent passes. I missed this before (thanks, Eli). I tried adding the explicit move patterns, and at least it compiles correctly now: i1_ls: R0.H = HI(i1_l); R0.L = LO(i1_l); P0 = R...

...hine value type. >> >> The x86 backend has an example of a partial solution. The GR32 >> register class has a subset, GR32_, which is the registers in GR32 >> that support 8-bit subregs. Instructions that reference 8-bit >> subregs >> are emitted with a copy (MOV32to32_) to put the value in a virtual >> register of the needed class. This copy may then optimized away >> by subsequent passes. > > I missed this before (thanks, Eli). I tried adding the explicit move > patterns, and at least it compiles correctly now: > > i1_ls: > R0.H...

...ends seem to have only one > register class per machine value type. The x86 backend has an example of a partial solution. The GR32 register class has a subset, GR32_, which is the registers in GR32 that support 8-bit subregs. Instructions that reference 8-bit subregs are emitted with a copy (MOV32to32_) to put the value in a virtual register of the needed class. This copy may then optimized away by subsequent passes. Right now the x86 target code has to explicitly spell out where such copies are needed. It isn't a lot of trouble because there are a small number of situations where copies a...

Hi, I am writing a backend for the Blackfin processor from Analog Devices. I just started so I still have a lot to learn about the code generator. So far, I can compile test/CodeGen/Generic/BasicInstrs.ll correctly, but that is about it. The Blackfin 32-bit registers divide naturally into several classes. I have modelled these register classes without knowing anything about what the code

Hi Anton and Dale first thanks for your answers. On 8 Aug 2007, at 16:43, Anton Korobeynikov wrote: > Hello, Arnold. > >> Is there a way to indicate that the register the tail call >> instruction uses as destination needs to be valid after the callee >> saved registers have been restored? (some X86InstrInfo.td foo magic >> maybe ?) > It's wrong way to do the

Hello, Arnold. > Is there a way to indicate that the register the tail call > instruction uses as destination needs to be valid after the callee > saved registers have been restored? (some X86InstrInfo.td foo magic > maybe ?) It's wrong way to do the things. Because in this case you either violate the ABI for callee, or you're restricted to do tail call lowering only for