search for: mov32mi

I have tested the register allocation in llvm, using: $llc -debug test.bc where, test.c is like: int a, b, c, d, x; a = 3; b = 5; d = 4; x = 100; if ( a > b ) ...... And I got the machine code before register allocation: MOV32mi <fi#2>, 1, %reg0, 0, %reg0, 3; mem:ST4[%a] MOV32mi <fi#3>, 1, %reg0, 0, %reg0, 5; mem:ST4[%b] MOV32mi <fi#5>, 1, %reg0, 0, %reg0, 4; mem:ST4[%d] MOV32mi <fi#6>, 1, %reg0, 0, %reg0, 100; mem:ST4[%x] %reg16384<def> = MOV32rm <fi#3>,...

...seteq int %9, 0 ; <bool>:7 [#uses=1] br bool %7, label %entry.bb19_crit_edge.i270, label %bb.preheader.i271 It gets converted to the following MachineBasicBlock __exp.exit (0x8c58628, LLVM BB @0x8c1c558, ID#21): Predecessors according to CFG: 0x8c53a90 0x8c55b50 MOV32mi %EBP, 1, %NOREG, -224, <ga:DataStore> %EAX = MOV32rm %EBP, 1, %NOREG, -224 %EAX = ADD32ri8 %EAX, 40 MOV32mi %EAX, 1, %NOREG, 0, 0 MOV32mi %EAX, 1, %NOREG, 4, 1075576832 %ESP = SUB32ri %ESP, 16 %XMM0 = CVTSI2SDrr %EDI MOVSDmr %ESP, 1, %NO...

...es with SFI validation rules by re-implementing SFI for the LLVM x86 backend based on the Google NaCl project. However, in trying to implement 32-byte code alignment, X86InstrInfo::GetInstSizeInBytes() is returning incorrect instruction sizes for certain instructions (that I have seen so far): MOV32mi, LEA32r, MOV32mr, and MOV32rm. MOV32mi is always calculated incorrectly while the remaining 3 are sometimes calculated incorrectly. Just to illustrate: 8d 9c 24 30 0a 00 00 LEA32r calculated length: 7 ok 8d 6c 24 28...

...issue? I don't have another computer I can test this on to see if that's it though. If this turns out to be a bug, rather than some misuse/misinterpretation of the function on my part I can resubmit it via that channel. The instructions I've noticed this occurring for are: MOV32mi, LEA32r, MOV32mr, and MOV32rm The length of LEA32r is calculated correctly some of the time. Same for MOV32mr and MOV32rm. The length of MOV32mi seems to always be wrong. An example breakdown of emitted Machine Instructions - the machine instructions are those outputted when I pass the...

...k>, %RSP<imp-use>, %AL<imp-use,kill>, %RDI<imp-use,kill>, %EAX<imp-def> ADJCALLSTACKUP64 0, 0, %RSP<imp-def>, %EFLAGS<imp-def>, %RSP<imp-use> MOV32mr <fi#6>, 1, %noreg, 0, %noreg, %EAX<kill>; mem:ST4[FixedStack6] JMP_4 <BB#3> entry BB#0 MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0 MOV32mr <fi#1>, 1, %noreg, 0, %noreg, %EDI<kill> MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %RSI<kill> MOV32mi <fi#3>, 1, %noreg, 0, %noreg, 0 MOV32mi <fi#4>, 1, %noreg, 0, %noreg, 4 %EDI<def> = MOV32rm <fi#3>, 1, %nor...

Hi, I'm having some trouble wirting an instruction in the X86 backend. I made a new intrinsic and I wrote a custom inserter for my intrinsic in the X86 backend. Everything works fine, except for one instruction that I can't find how to write. I want to add this instruction in one of my machine basic block: mov [rdi], 0 How can I achieve that with the LLVM api? I tried several

The following is the code fragment after "# *** IR Dump Before Prolog/Epilog Insertion & Frame Finalization ***:". * MOV32mi <fi#2>, 1, %reg0, 0, %reg0, 0 * * MOV32mr <fi#2>, 1, %reg0, 0, %reg0, %ECX<kill>* * %EAX<def> = MOV32rm <fi#2>, 1, %reg0, 0, %reg0* * MOV32mr %reg0, 1, %reg0, <ga:@one+4>, %reg0, %EAX<kill>* * %EAX<def> = MOV32rm <fi#2>, 1, %reg0, 0, %reg0* * AD...

...%BPL %BX %DI %DIL %EBP %EBX %EDI %ESI %SI %SIL>, %ESP<imp-use>, %ESP<imp-def>, %EAX<imp-def,dead>, %EDX<imp-def,dead> %ESP<def,tied1> = ADD32ri8 %ESP<tied0>, 4, %EFLAGS<imp-def,dead> CFI_INSTRUCTION <call frame instruction> MOV32mi %noreg, 1, %noreg, <ga:@foo>, %noreg, <ga:@JazzFixnumClass>; mem:ST4[getelementptr inbounds ({ i8*, i32 }, { i8*, i32 }* @foo, i32 0, i32 0)] PUSHi32 <ga:@foo+4>, %ESP<imp-def>, %ESP<imp-use> CFI_INSTRUCTION <call frame instruction> CALLpc...

llvm/lib/Target/X86/X86InstrInfo.td: class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string AsmStr> : Instruction { .... dag OperandList = ops; string AsmString = AsmStr; } def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src), "mov{l} {$src, $dst|$dst, $src}">; I cannot find any document on initializing the 'dag' type variable, and I cannot understand the syntax of "asmstring" either. how does the x86 asmwrite inter...

...ng the wrong thing somewhere. The assembly code generated for the function is: BB#0: derived from LLVM BB %entry %RSP<def> = SUB64ri8 %RSP, 24, %EFLAGS<imp-def,dead>; dbg:l8.cpp:1:1 PROLOG_LABEL <MCSym=.Ltmp0>; dbg:l8.cpp:1:1 DBG_VALUE %EDI, 0, !"arg1"; dbg:l8.cpp:3:1 MOV32mi %RSP, 1, %reg0, 20, %reg0, 21; mem:ST4[%X] dbg:l8.cpp:1:1 MOV32mi %RSP, 1, %reg0, 16, %reg0, 22; mem:ST4[%Y] dbg:l8.cpp:1:1 MOV32mi %RSP, 1, %reg0, 12, %reg0, 23; mem:ST4[%Z] dbg:l8.cpp:1:1 %EDI<def> = MOV32rm %RSP, 1, %reg0, 20, %reg0; mem:LD4[%X] dbg:l8.cpp:1:1 MOV32mr %RSP, 1, %reg0, 12, %...

Hi, I had (naively?) expected that the instruction to move immediate to register or memory (such as MOV32mi, MOV32ri, MOV64mi32, MOV64ri, MOV64ri32) would be marked with the flag MCID::MovImm via the X86InstrInfo.td (and hence in the generated X86GenInstrInfo.inc). I do not see that to be the case. Can someone please tell me if my expectation is flawed? Is there a better/different way to determine to t...

...eg1024, 1, %NOREG, 0 %reg1026 = MOVSX32rm8 %reg1025, 1, %NOREG, 0 %reg1027 = MOVSX32rm8 %reg1025, 1, %NOREG, 1 ADJCALLSTACKDOWN 8 %reg1028 = ADD32rr %reg1026, %reg1027 %reg1029 = IMUL32rr %reg1028, %reg1027 MOV32mr %ESP, 1, %NOREG, 4, %reg1029 MOV32mi %ESP, 1, %NOREG, 0, <ga:.str_1> CALLpcrel32 <ga:printf> ADJCALLSTACKUP 8, 0 %reg1030 = MOV32rr %EAX %reg1031 = IMPLICIT_DEF_GR32 %EAX = MOV32rr %reg1031 RET My allocator produces this mapping: FNSTCW16m := MOV8mi...

...f> = COPY %RSI; GR64:%vreg2 %vreg0<def> = COPY %EDI; GR32:%vreg0 %vreg1<def> = COPY %vreg0<kill>; GR32:%vreg1,%vreg0 %vreg3<def> = COPY %vreg2<kill>; GR64:%vreg3,%vreg2 %vreg5<def> = MOV64ri <ga:@.str>; GR64:%vreg5 MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 0; mem:ST4[%retval] MOV32mr <fi#1>, 1, %noreg, 0, %noreg, %vreg1; mem:ST4[%argc.addr] GR32:%vreg1 MOV64mr <fi#2>, 1, %noreg, 0, %noreg, %vreg3; mem:ST8[%argv.addr] GR64:%vreg3 ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS&...

...trying to do? > > ~Craig > > On Fri, Feb 9, 2018 at 11:45 AM, S. Bharadwaj Yadavalli via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > >> Hi, >> >> I had (naively?) expected that the instruction to move immediate to >> register or memory (such as MOV32mi, MOV32ri, MOV64mi32, MOV64ri, >> MOV64ri32) would be marked with the flag MCID::MovImm via the >> X86InstrInfo.td (and hence in the generated X86GenInstrInfo.inc). >> >> I do not see that to be the case. >> >> Can someone please tell me if my expectation is flawe...

On Fri, 6 May 2005, Tzu-Chien Chiu wrote: > llvm/lib/Target/X86/X86InstrInfo.td: > class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string > AsmStr> : Instruction { > .... > dag OperandList = ops; > string AsmString = AsmStr; > } > > def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src), > "mov{l} {$src, $dst|$dst, $src}">; > > I cannot find any document on initializing the 'dag' type variable, > and I cannot understand the syntax of "asmstring" either. The DAG opera...

...SI %SI %SIL>, %ESP<imp-use>, %ESP<imp-def>, >> %EAX<imp-def,dead>, %EDX<imp-def,dead> >> %ESP<def,tied1> = ADD32ri8 %ESP<tied0>, 4, %EFLAGS<imp-def,dead> >> CFI_INSTRUCTION <call frame instruction> >> MOV32mi %noreg, 1, %noreg, <ga:@foo>, %noreg, >> <ga:@JazzFixnumClass>; mem:ST4[getelementptr inbounds ({ i8*, i32 }, { >> i8*, i32 }* @foo, i32 0, i32 0)] >> PUSHi32 <ga:@foo+4>, %ESP<imp-def>, %ESP<imp-use> >> CFI_INSTRUCTION <call...

...the flag on any instructions What are you trying to do? ~Craig On Fri, Feb 9, 2018 at 11:45 AM, S. Bharadwaj Yadavalli via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Hi, > > I had (naively?) expected that the instruction to move immediate to > register or memory (such as MOV32mi, MOV32ri, MOV64mi32, MOV64ri, > MOV64ri32) would be marked with the flag MCID::MovImm via the > X86InstrInfo.td (and hence in the generated X86GenInstrInfo.inc). > > I do not see that to be the case. > > Can someone please tell me if my expectation is flawed? Is there a > bette...

...(MBB_erase); BuildMI(*MBB_cond, MBB_cond->end(), db, TII->get(X86::CMP64rr)).addReg(regB).addReg(X86::RBP); BuildMI(*MBB_cond, MBB_cond->end(), db, TII->get(X86::JE_4)).addMBB(MBB_end); // mov dword[reg], 0x0 BuildMI(*MBB_erase, MBB_erase->end(), db, TII->get(X86::MOV32mi)).addReg(regB).addImm(1).addReg(0).addImm(0).addReg(0).addImm(0); BuildMI(*MBB_erase, MBB_erase->end(), db, TII->get(X86::ADD64ri32), regC).addReg(regB).addImm(8); BuildMI(*MBB_cond, MBB_erase->end(), db, TII->get(X86::JMP_4)).addMBB(MBB_cond); // Erase intrinsic MI->...

...> > llvm/lib/Target/X86/X86InstrInfo.td: > > class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string > > AsmStr> : Instruction { > > .... > > dag OperandList = ops; > > string AsmString = AsmStr; > > } > > > > def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src), > > "mov{l} {$src, $dst|$dst, $src}">; > > > > I cannot find any document on initializing the 'dag' type variable, > > and I cannot understand the syntax of "asmstring" ei...

...MBB_cond->end(), db, TII->get(X86::JE_4)).addMBB(MBB_end); // Update phi node BuildMI(*MBB_erase, MBB_erase->end(), db, TII->get(X86::PHI), reg).addReg(reg).addMBB(MBB).addReg(reg).addMBB(MBB_erase); // Erase content of stack BuildMI(*MBB_erase, MBB_erase->end(), db, TII->get(X86::MOV32mi)) .addReg(reg).addImm(1).addReg(0).addImm(0).addReg(0) .addImm(0); // Increment loop variable and jmp BuildMI(*MBB_erase, MBB_erase->end(), db, TII->get(X86::ADD64ri32), reg).addReg(reg).addImm(8); BuildMI(*MBB_erase, MBB_erase->end(), db, TII->get(X86::JMP_4)).addMBB(MBB_cond); // Eras...