Displaying 20 results from an estimated 45 matches for "mov32".
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mov2
2014 Oct 27
5
[PATCH v12 09/11] pvqspinlock, x86: Add para-virtualization support
...avirt_patch_64.c
> ===================================================================
> --- linux-2.6.orig/arch/x86/kernel/paravirt_patch_64.c
> +++ linux-2.6/arch/x86/kernel/paravirt_patch_64.c
> @@ -22,6 +22,10 @@ DEF_NATIVE(pv_cpu_ops, swapgs, "swapgs")
> DEF_NATIVE(, mov32, "mov %edi, %eax");
> DEF_NATIVE(, mov64, "mov %rdi, %rax");
>
> +#if defined(CONFIG_PARAVIRT_SPINLOCKS)&& defined(CONFIG_QUEUE_SPINLOCK)
> +DEF_NATIVE(pv_lock_ops, queue_unlock, "movb $0, (%rdi)");
> +#endif
> +
> unsigned paravirt_pa...
2014 Oct 27
5
[PATCH v12 09/11] pvqspinlock, x86: Add para-virtualization support
...avirt_patch_64.c
> ===================================================================
> --- linux-2.6.orig/arch/x86/kernel/paravirt_patch_64.c
> +++ linux-2.6/arch/x86/kernel/paravirt_patch_64.c
> @@ -22,6 +22,10 @@ DEF_NATIVE(pv_cpu_ops, swapgs, "swapgs")
> DEF_NATIVE(, mov32, "mov %edi, %eax");
> DEF_NATIVE(, mov64, "mov %rdi, %rax");
>
> +#if defined(CONFIG_PARAVIRT_SPINLOCKS)&& defined(CONFIG_QUEUE_SPINLOCK)
> +DEF_NATIVE(pv_lock_ops, queue_unlock, "movb $0, (%rdi)");
> +#endif
> +
> unsigned paravirt_pa...
2017 Oct 25
0
[PATCH 03/13] x86/paravirt: Convert native patch assembly code strings to macros
...NGLE);
>
> -DEF_NATIVE(pv_cpu_ops, usergs_sysret64, "swapgs; sysretq");
> -DEF_NATIVE(pv_cpu_ops, swapgs, "swapgs");
> +DEF_NATIVE(pv_cpu_ops, usergs_sysret64, NATIVE_USERGS_SYSRET64);
> +DEF_NATIVE(pv_cpu_ops, swapgs, NATIVE_SWAPGS);
>
> -DEF_NATIVE(, mov32, "mov %edi, %eax");
> -DEF_NATIVE(, mov64, "mov %rdi, %rax");
> +DEF_NATIVE(, mov32, NATIVE_IDENTITY_32);
> +DEF_NATIVE(, mov64, NATIVE_IDENTITY);
>
> #if defined(CONFIG_PARAVIRT_SPINLOCKS)
> -DEF_NATIVE(pv_lock_ops, queued_spin_unlock, "movb $0,...
2014 Oct 27
2
[PATCH v12 09/11] pvqspinlock, x86: Add para-virtualization support
...=========================================================
>>> --- linux-2.6.orig/arch/x86/kernel/paravirt_patch_64.c
>>> +++ linux-2.6/arch/x86/kernel/paravirt_patch_64.c
>>> @@ -22,6 +22,10 @@ DEF_NATIVE(pv_cpu_ops, swapgs, "swapgs")
>>> DEF_NATIVE(, mov32, "mov %edi, %eax");
>>> DEF_NATIVE(, mov64, "mov %rdi, %rax");
>>>
>>> +#if defined(CONFIG_PARAVIRT_SPINLOCKS)&& defined(CONFIG_QUEUE_SPINLOCK)
>>> +DEF_NATIVE(pv_lock_ops, queue_unlock, "movb $0, (%rdi)");
>>> +...
2014 Oct 27
2
[PATCH v12 09/11] pvqspinlock, x86: Add para-virtualization support
...=========================================================
>>> --- linux-2.6.orig/arch/x86/kernel/paravirt_patch_64.c
>>> +++ linux-2.6/arch/x86/kernel/paravirt_patch_64.c
>>> @@ -22,6 +22,10 @@ DEF_NATIVE(pv_cpu_ops, swapgs, "swapgs")
>>> DEF_NATIVE(, mov32, "mov %edi, %eax");
>>> DEF_NATIVE(, mov64, "mov %rdi, %rax");
>>>
>>> +#if defined(CONFIG_PARAVIRT_SPINLOCKS)&& defined(CONFIG_QUEUE_SPINLOCK)
>>> +DEF_NATIVE(pv_lock_ops, queue_unlock, "movb $0, (%rdi)");
>>> +...
2017 Oct 04
1
[PATCH 03/13] x86/paravirt: Convert native patch assembly code strings to macros
...ush_tlb_single, NATIVE_FLUSH_TLB_SINGLE);
-DEF_NATIVE(pv_cpu_ops, usergs_sysret64, "swapgs; sysretq");
-DEF_NATIVE(pv_cpu_ops, swapgs, "swapgs");
+DEF_NATIVE(pv_cpu_ops, usergs_sysret64, NATIVE_USERGS_SYSRET64);
+DEF_NATIVE(pv_cpu_ops, swapgs, NATIVE_SWAPGS);
-DEF_NATIVE(, mov32, "mov %edi, %eax");
-DEF_NATIVE(, mov64, "mov %rdi, %rax");
+DEF_NATIVE(, mov32, NATIVE_IDENTITY_32);
+DEF_NATIVE(, mov64, NATIVE_IDENTITY);
#if defined(CONFIG_PARAVIRT_SPINLOCKS)
-DEF_NATIVE(pv_lock_ops, queued_spin_unlock, "movb $0, (%rdi)");
-DEF_NATIVE(pv_...
2013 Oct 26
2
[LLVMdev] Add support for ldr pseudo instruction in ARM integrated assembler
...ad is a plain move instruction or a memory reference. That
makes it very difficult to read the assembly and do any sort of thinking
about performance considerations.
I believe that the ldr pseudo will always expand to a single instruction
(mov, movn, or ldr). I see that armasm also supports a mov32 pseudo
instruction that expands to movw/movt pair. GCC does not support mov32 and
Im not proposing that we add it to llvm.
We have been trying to deprecate pre-UAL and GNU-extensions as much as
possible, and this is a move that is supported from most of the ARM LLVM
community. The main reason...
2013 Oct 29
0
[LLVMdev] Add support for ldr pseudo instruction in ARM integrated assembler
...plain ‘move’ instruction or a memory reference. That makes it very difficult to read the assembly and do any sort of thinking about performance considerations.
>
> I believe that the ldr pseudo will always expand to a single instruction (mov, movn, or ldr). I see that armasm also supports a mov32 pseudo instruction that expands to movw/movt pair. GCC does not support mov32 and I’m not proposing that we add it to llvm.
>
OK. If we can restrict this to always only generating a single instruction, I’m less concerned. Still not a huge fan, but not actively opposed. Thanks for checking into...
2014 Oct 24
0
[PATCH v12 09/11] pvqspinlock, x86: Add para-virtualization support
...ux-2.6/arch/x86/kernel/paravirt_patch_64.c
===================================================================
--- linux-2.6.orig/arch/x86/kernel/paravirt_patch_64.c
+++ linux-2.6/arch/x86/kernel/paravirt_patch_64.c
@@ -22,6 +22,10 @@ DEF_NATIVE(pv_cpu_ops, swapgs, "swapgs")
DEF_NATIVE(, mov32, "mov %edi, %eax");
DEF_NATIVE(, mov64, "mov %rdi, %rax");
+#if defined(CONFIG_PARAVIRT_SPINLOCKS) && defined(CONFIG_QUEUE_SPINLOCK)
+DEF_NATIVE(pv_lock_ops, queue_unlock, "movb $0, (%rdi)");
+#endif
+
unsigned paravirt_patch_ident_32(void *insnbuf, unsigne...
2014 Oct 27
0
[PATCH v12 09/11] pvqspinlock, x86: Add para-virtualization support
...; >===================================================================
> >--- linux-2.6.orig/arch/x86/kernel/paravirt_patch_64.c
> >+++ linux-2.6/arch/x86/kernel/paravirt_patch_64.c
> >@@ -22,6 +22,10 @@ DEF_NATIVE(pv_cpu_ops, swapgs, "swapgs")
> > DEF_NATIVE(, mov32, "mov %edi, %eax");
> > DEF_NATIVE(, mov64, "mov %rdi, %rax");
> >
> >+#if defined(CONFIG_PARAVIRT_SPINLOCKS)&& defined(CONFIG_QUEUE_SPINLOCK)
> >+DEF_NATIVE(pv_lock_ops, queue_unlock, "movb $0, (%rdi)");
> >+#endif
> >+
&g...
2014 Oct 27
0
[PATCH v12 09/11] pvqspinlock, x86: Add para-virtualization support
...; >===================================================================
> >--- linux-2.6.orig/arch/x86/kernel/paravirt_patch_64.c
> >+++ linux-2.6/arch/x86/kernel/paravirt_patch_64.c
> >@@ -22,6 +22,10 @@ DEF_NATIVE(pv_cpu_ops, swapgs, "swapgs")
> > DEF_NATIVE(, mov32, "mov %edi, %eax");
> > DEF_NATIVE(, mov64, "mov %rdi, %rax");
> >
> >+#if defined(CONFIG_PARAVIRT_SPINLOCKS)&& defined(CONFIG_QUEUE_SPINLOCK)
> >+DEF_NATIVE(pv_lock_ops, queue_unlock, "movb $0, (%rdi)");
> >+#endif
> >+
&g...
2014 Oct 29
0
[PATCH v12 09/11] pvqspinlock, x86: Add para-virtualization support
...=========================================
>>>> --- linux-2.6.orig/arch/x86/kernel/paravirt_patch_64.c
>>>> +++ linux-2.6/arch/x86/kernel/paravirt_patch_64.c
>>>> @@ -22,6 +22,10 @@ DEF_NATIVE(pv_cpu_ops, swapgs, "swapgs")
>>>> DEF_NATIVE(, mov32, "mov %edi, %eax");
>>>> DEF_NATIVE(, mov64, "mov %rdi, %rax");
>>>>
>>>> +#if defined(CONFIG_PARAVIRT_SPINLOCKS)&&
>>>> defined(CONFIG_QUEUE_SPINLOCK)
>>>> +DEF_NATIVE(pv_lock_ops, queue_unlock, "movb...
2015 Nov 18
0
[PATCH 3/3] x86: usergs_sysret32 pv op is no longer needed
...cpu_ops, clts, "clts");
DEF_NATIVE(pv_cpu_ops, wbinvd, "wbinvd");
DEF_NATIVE(pv_cpu_ops, usergs_sysret64, "swapgs; sysretq");
-DEF_NATIVE(pv_cpu_ops, usergs_sysret32, "swapgs; sysretl");
DEF_NATIVE(pv_cpu_ops, swapgs, "swapgs");
DEF_NATIVE(, mov32, "mov %edi, %eax");
@@ -54,7 +53,6 @@ unsigned native_patch(u8 type, u16 clobbers, void *ibuf,
PATCH_SITE(pv_irq_ops, save_fl);
PATCH_SITE(pv_irq_ops, irq_enable);
PATCH_SITE(pv_irq_ops, irq_disable);
- PATCH_SITE(pv_cpu_ops, usergs_sysret32);
PATCH_SITE(pv_cpu_ops, usergs_sy...
2015 Mar 16
0
[PATCH 9/9] qspinlock, x86, kvm: Implement KVM support for paravirt qspinlock
...en);
break;
+
+ patch_site:
+ ret = paravirt_patch_insns(ibuf, len, start, end);
+ break;
}
#undef PATCH_SITE
return ret;
--- a/arch/x86/kernel/paravirt_patch_64.c
+++ b/arch/x86/kernel/paravirt_patch_64.c
@@ -21,6 +21,10 @@ DEF_NATIVE(pv_cpu_ops, swapgs, "swapgs")
DEF_NATIVE(, mov32, "mov %edi, %eax");
DEF_NATIVE(, mov64, "mov %rdi, %rax");
+#if defined(CONFIG_PARAVIRT_SPINLOCKS) && defined(CONFIG_QUEUE_SPINLOCK)
+DEF_NATIVE(pv_lock_ops, queue_spin_unlock, "movb $0, (%rdi)");
+#endif
+
unsigned paravirt_patch_ident_32(void *insnbuf, un...
2015 Mar 16
0
[PATCH 9/9] qspinlock, x86, kvm: Implement KVM support for paravirt qspinlock
...en);
break;
+
+ patch_site:
+ ret = paravirt_patch_insns(ibuf, len, start, end);
+ break;
}
#undef PATCH_SITE
return ret;
--- a/arch/x86/kernel/paravirt_patch_64.c
+++ b/arch/x86/kernel/paravirt_patch_64.c
@@ -21,6 +21,10 @@ DEF_NATIVE(pv_cpu_ops, swapgs, "swapgs")
DEF_NATIVE(, mov32, "mov %edi, %eax");
DEF_NATIVE(, mov64, "mov %rdi, %rax");
+#if defined(CONFIG_PARAVIRT_SPINLOCKS) && defined(CONFIG_QUEUE_SPINLOCK)
+DEF_NATIVE(pv_lock_ops, queue_spin_unlock, "movb $0, (%rdi)");
+#endif
+
unsigned paravirt_patch_ident_32(void *insnbuf, un...
2015 Apr 30
0
[PATCH 4/6] x86: introduce new pvops function spin_unlock
...4.c
@@ -1,5 +1,6 @@
#include <asm/paravirt.h>
#include <asm/asm-offsets.h>
+#include <asm/spinlock.h>
#include <linux/stringify.h>
DEF_NATIVE(pv_irq_ops, irq_disable, "cli");
@@ -21,6 +22,14 @@ DEF_NATIVE(pv_cpu_ops, swapgs, "swapgs");
DEF_NATIVE(, mov32, "mov %edi, %eax");
DEF_NATIVE(, mov64, "mov %rdi, %rax");
+DEF_NATIVE(, unlock1, UNLOCK_LOCK_PREFIX
+ "addb $"__stringify(__TICKET_LOCK_INC)", (%rdi)");
+DEF_NATIVE(, unlock2, UNLOCK_LOCK_PREFIX
+ "addw $"__stringify(__TICKET_LOCK_INC)"...
2013 Oct 25
0
[LLVMdev] Add support for ldr pseudo instruction in ARM integrated assembler
On Oct 25, 2013, at 3:53 PM, David Peixotto <dpeixott at codeaurora.org> wrote:
> Hi Renato, Thanks for the thoughtful reply. Please find my thoughts below.
>
> -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
>
>
> From: Renato Golin [mailto:renato.golin at linaro.org]
> Sent: Friday, October 25, 2013 1:11 PM
2014 Jun 15
0
[PATCH 10/11] qspinlock: Paravirt support
...ux-2.6/arch/x86/kernel/paravirt_patch_64.c
===================================================================
--- linux-2.6.orig/arch/x86/kernel/paravirt_patch_64.c
+++ linux-2.6/arch/x86/kernel/paravirt_patch_64.c
@@ -22,6 +22,10 @@ DEF_NATIVE(pv_cpu_ops, swapgs, "swapgs")
DEF_NATIVE(, mov32, "mov %edi, %eax");
DEF_NATIVE(, mov64, "mov %rdi, %rax");
+#if defined(CONFIG_PARAVIRT_SPINLOCKS) && defined(CONFIG_QUEUE_SPINLOCK)
+DEF_NATIVE(pv_lock_ops, queue_unlock, "movb $0, (%rdi)");
+#endif
+
unsigned paravirt_patch_ident_32(void *insnbuf, unsigne...
2013 Oct 25
3
[LLVMdev] Add support for ldr pseudo instruction in ARM integrated assembler
Hi Renato, Thanks for the thoughtful reply. Please find my thoughts below.
-- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted
by The Linux Foundation
From: Renato Golin [mailto:renato.golin at linaro.org]
Sent: Friday, October 25, 2013 1:11 PM
To: David Peixotto
Cc: LLVM Dev; Logan Chien; Gabor Ballabas; Rafael Espíndola; Richard Barton;
Amara Emerson
Subject:
2017 Oct 04
31
[PATCH 00/13] x86/paravirt: Make pv ops code generation more closely match reality
This changes the pv ops code generation to more closely match reality.
For example, instead of:
callq *0xffffffff81e3a400 (pv_irq_ops.save_fl)
vmlinux will now show:
pushfq
pop %rax
nop
nop
nop
nop
nop
which is what the runtime version of the code will show in most cases.
This idea was suggested by Andy Lutomirski.
The benefits are:
- For the most common runtime cases