Displaying 6 results from an estimated 6 matches for "mov16".
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2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...lt;asmstr, srcAReg, memhx,
[(directStore (dstType (OpNode
srcAReg:$srcA)), addr16:$dstD)]>;
def MEM_MEM : SetADIn<asmstr, memhx, memhx,
[(directStore (dstType (OpNode (srcAType
(load addr16:$srcA)))), addr16:$dstD)]>;
}
defm MOV16Copy_ : AD<"mov16", null_frag, GPRBaseRegs, GPRBaseRegs,
i16, i16, simm16, immSExt16x>;
On Tue, Aug 25, 2015 at 1:02 PM, Ryan Taylor <ryta1203 at gmail.com> wrote:
> Quentin,
>
> 1. I'll take a look, it's also picking the reg class by the
> SimpleV...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
1. MOV16Copy_IMM_REG is the instruction matched, sorry. AD is the
multiclass. The IMM in my case is a global. So you can see that
GPRBaseRegs, GPRBaseRegs sets the registerclass for both the src and dst
operands, in this case (MOV16Copy_IMM_REG) it's the dst.
2. Yes I agree, it most likely would.
Hone...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...for that instruction, it should use that regclass
or subregclasses (depending on use/def info), correct?
On Tue, Aug 25, 2015 at 1:37 PM, Quentin Colombet <qcolombet at apple.com>
wrote:
>
> On Aug 25, 2015, at 10:29 AM, Ryan Taylor <ryta1203 at gmail.com> wrote:
>
> 1. MOV16Copy_IMM_REG is the instruction matched, sorry. AD is the
> multiclass. The IMM in my case is a global. So you can see that
> GPRBaseRegs, GPRBaseRegs sets the registerclass for both the src and dst
> operands, in this case (MOV16Copy_IMM_REG) it's the dst.
>
> 2. Yes I agree, it...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...what I can tell you.
>
> Cheers,
> -Quentin
>
>
>
>
>
> On Tue, Aug 25, 2015 at 1:37 PM, Quentin Colombet <qcolombet at apple.com>
> wrote:
>
>>
>> On Aug 25, 2015, at 10:29 AM, Ryan Taylor <ryta1203 at gmail.com> wrote:
>>
>> 1. MOV16Copy_IMM_REG is the instruction matched, sorry. AD is the
>> multiclass. The IMM in my case is a global. So you can see that
>> GPRBaseRegs, GPRBaseRegs sets the registerclass for both the src and dst
>> operands, in this case (MOV16Copy_IMM_REG) it's the dst.
>>
>>...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
BB#0: derived from LLVM BB %entry
%vreg0<def> = MOV16Copy_IMM_REG <ga:@a+1>[TF=1]; GPRRegs:%vreg0
%vreg1<def> = COPY %vreg0; PTRRegs:%vreg1 GPRRegs:%vreg0
Send_iii %NULLR0, %vreg1<kill>, 1, 1, 1, 1, 0; PTRRegs:%vreg1
RetRA
This is what I get. This is what I'd like to get:
BB#0: derived from LLVM BB %entry
%vreg0<def&...
2015 Aug 25
4
[LLVMdev] TableGen Register Class not matching for MI in 3.6
Hi Ryan,
> On Aug 24, 2015, at 6:49 PM, Ryan Taylor <ryta1203 at gmail.com> wrote:
>
> Quentin,
>
> I apologize for the spamming here but in getVR (where VReg is assigned an RC), it calls:
>
> const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getSimpleValueType());
> VReg = MRI->createVirtualRegister(RC);
>
> My question is why is it using the