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...hether MachineInstrBundles might be a neater solution but I wasn't sure whether they were really intended, or suitable, for this purpose. Steve On 3 Jun 2013, at 17:30, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > > On Jun 3, 2013, at 6:05 AM, Steve Montgomery <stephen.montgomery3 at btinternet.com> wrote: > >> I'm working on an out-of-tree target and am having some problems with rematerialization and spilling. >> >> The target's load and store instructions affect the condition code register (CCR). Describing this in the InstrInfo.td file us...

Sorry, forgot to Reply-All. Begin forwarded message: > From: Steve Montgomery <stephen.montgomery3 at btinternet.com> > Subject: Re: [LLVMdev] Prevention register promotion at the isel codegen phase > Date: 24 November 2012 17:09:58 GMT > To: Joseph Pusdesris <joe at pusdesris.com> > > I had a similar problem trying to implement reg-mem operations. The solution I chose w...

Yes, this is very helpful! Thank you! How does this work when exiting a variable's liveness range? Will it automatically know to free the stack slot for reuse? -Joe On Sat, Nov 24, 2012 at 12:23 PM, Steve Montgomery < stephen.montgomery3 at btinternet.com> wrote: > Sorry, forgot to Reply-All. > > Begin forwarded message: > > *From: *Steve Montgomery <stephen.montgomery3 at btinternet.com> > *Subject: **Re: [LLVMdev] Prevention register promotion at the isel > codegen phase* > *Date: *24 November 20...

...ror of my ways :) I’m guessing that I need to check that the offset operand is truly a 16-bit register and return false if it isn’t. A nice simple fix if that is all that is needed - thanks again for shedding light on this for me. MartinO From: Steve Montgomery [mailto:stephen.montgomery3 at btinternet.com] Sent: 02 November 2015 20:25 To: Martin J. O'Riordan <martin.oriordan at movidius.com> Cc: LLVM Developers <llvm-dev at lists.llvm.org> Subject: Re: [llvm-dev] Questions about load/store incrementing address modes On 2 Nov 2015, at 10:27, Martin J. O'R...

I forgot to mention that I used EXTRACT_ELEMENT in my backend to get the high and low parts of an SDValue. On 10 Nov 2013, at 17:50, Steve Montgomery <stephen.montgomery3 at btinternet.com> wrote: > I had a similar problem with a backend for the 68HC12 family which also has no barrel shifter. Some 68HC12 CPUs support shift for just one of the 16-bit registers and only support rotation on the 2 8-bit subregs of that 16-bit register. That means the only practic...

On Jun 3, 2013, at 9:42 AM, Steve Montgomery <stephen.montgomery3 at btinternet.com> wrote: > I can use pseudo-instructions to bundle cmp+jump but it's not ideal because I might also have to bundle cmp+jump+jump+... into a pseudo. That may not be necessary. The register allocator won’t insert anything between terminators. /jakob

...xample for me at times). Could I also ask whether you had to design your shift nodes with Glue or Chain operands? I haven't taken extra that step yet, but I imagine it will be necessary. Sincerely, ~Dave Waggoner / MathOnNapkins On Sun, Nov 10, 2013 at 1:35 PM, Steve Montgomery < stephen.montgomery3 at btinternet.com> wrote: > I forgot to mention that I used EXTRACT_ELEMENT in my backend to get the > high and low parts of an SDValue. > > On 10 Nov 2013, at 17:50, Steve Montgomery < > stephen.montgomery3 at btinternet.com> wrote: > > > I had a similar problem w...

On Jun 3, 2013, at 9:42 AM, Steve Montgomery <stephen.montgomery3 at btinternet.com> wrote: > Hi Jakob, > > thanks for the advice. I'll do as you suggest and make sure that CCR is never live. > > I can use pseudo-instructions to bundle cmp+jump but it's not ideal because I might also have to bundle cmp+jump+jump+... into a pseudo. Als...

On Jun 3, 2013, at 6:05 AM, Steve Montgomery <stephen.montgomery3 at btinternet.com> wrote: > I'm working on an out-of-tree target and am having some problems with rematerialization and spilling. > > The target's load and store instructions affect the condition code register (CCR). Describing this in the InstrInfo.td file using Defs = [CCR]...

I've been working on a backend for a 16-bit microcontroller and I've just updated my base from LLVM 3.4 to LLVM 3.5.0. This threw up a regression failure in my test suite, and having tracked down the cause, I'm now confused about the DAG legalization and optimization process which I thought I understood. I'd be really grateful for advice on whether I've misunderstood how

I'm working on an out-of-tree target and am having some problems with rematerialization and spilling. The target's load and store instructions affect the condition code register (CCR). Describing this in the InstrInfo.td file using Defs = [CCR] certainly prevents spills and fills from being inserted where they might clobber CCR but it also prevents the load instruction from being

...du/pipermail/llvm-commits/Week-of-Mon-20120507/142659.html) I would recommend trying something like Sergei's solution first, and fall back to trying to play with the critical chain only if that can't or won't work. -Hal On Mon, 13 Aug 2012 11:29:18 +0100 Steve Montgomery <stephen.montgomery3 at btinternet.com> wrote: > I've got a question about how SelectionDAGBuilder treats loads. > > The LLVM Language Reference Manual explicitly states that the order > of volatile operations may be changed relative to non-volatile > operations. However, when the SelectionDAGBu...

...07/142659.html) > > I would recommend trying something like Sergei's solution first, and > fall back to trying to play with the critical chain only if that can't > or won't work. > > -Hal > > On Mon, 13 Aug 2012 11:29:18 +0100 > Steve Montgomery <stephen.montgomery3 at btinternet.com> wrote: > >> I've got a question about how SelectionDAGBuilder treats loads. >> >> The LLVM Language Reference Manual explicitly states that the order >> of volatile operations may be changed relative to non-volatile >> operations. However...

...1 = *(i0 += m0). So increment i0 by m0. Read memory the memory location "pointed" to by i0. Store in r1. Sadly I am not too familiar with compiler terminology, so I don't know if there is a proper term for such a load. On Thu, Oct 23, 2014 at 12:23 PM, Steve Montgomery < stephen.montgomery3 at btinternet.com> wrote: > You might need to modify selectAddr so it doesn't fold the add node but > instead returns two operands: one for the pointer and one for the offset. > You can control the register classes for the two components of the address > using MIOperandInfo so y...

I've got a question about how SelectionDAGBuilder treats loads. The LLVM Language Reference Manual explicitly states that the order of volatile operations may be changed relative to non-volatile operations. However, when the SelectionDAGBuilder in LLVM 3.1 encounters a volatile load, it flushes all pending loads and then chains the volatile load onto them meaning that the volatile load must

...would recommend trying something like Sergei's solution first, and >> fall back to trying to play with the critical chain only if that can't >> or won't work. >> >> -Hal >> >> On Mon, 13 Aug 2012 11:29:18 +0100 >> Steve Montgomery <stephen.montgomery3 at btinternet.com> wrote: >> >>> I've got a question about how SelectionDAGBuilder treats loads. >>> >>> The LLVM Language Reference Manual explicitly states that the order >>> of volatile operations may be changed relative to non-volatile >>...

...nd"; let MIOperandInfo = (ops RC32, RC16_l); } but it is still happy to select for offset’s > 16-bits. There is something I am just not yet getting right, but it looks like I am on the right track. All the best, MartinO From: Steve Montgomery [mailto:stephen.montgomery3 at btinternet.com] Sent: 30 October 2015 13:47 To: Martin J. O'Riordan Cc: LLVM Developers Subject: Re: [llvm-dev] Questions about load/store incrementing address modes I’ve implemented something similar, though maybe not similar enough to be able to help you. My target supports increment...

On Aug 14, 2012, at 2:05 PM, Steve Montgomery <stephen.montgomery3 at btinternet.com> wrote: > Further to my earlier question, I'm perhaps a bit confused about memory serialisation. The following example, compiled using clang for the MSP430: > > target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16" > target triple = &qu...

...on the river and with reasonable beer and food. The Old Spring is also quite nice, has big tables outside, and is usually quite quiet midweek. David (Who has not yet completed the process of performing an exhaustive survey of Cambridge pubs) On 19 Jun 2013, at 16:46, Steve Montgomery <stephen.montgomery3 at btinternet.com> wrote: > Just cycled past The Fort. It's very busy because there's a fair on the common. Any plan B in case it's still full later? > > On 19 Jun 2013, at 15:20, Renato Golin <renato.golin at linaro.org> wrote: > >> Just a reminder, the Ca...

...mory location "pointed" to > by i0. Store in r1. Sadly I am not too familiar with compiler > terminology, so I don't know if there is a proper term for such a > load. > > > > > > > On Thu, Oct 23, 2014 at 12:23 PM, Steve Montgomery < > stephen.montgomery3 at btinternet.com > wrote: > > > You might need to modify selectAddr so it doesn't fold the add node > but instead returns two operands: one for the pointer and one for > the offset. You can control the register classes for the two > components of the address using MIOper...