search for: moll

On 2/2/19 1:39 AM, Luke Kenneth Casson Leighton wrote: > > > On Friday, February 1, 2019, Simon Moll <moll at cs.uni-saarland.de > <mailto:moll at cs.uni-saarland.de>> wrote: > > We could untie the mask length from the data length: > >   %result = call <scalable 4 x float> > @llvm.evl.fsub.v4f32(<scalable 4 x float> %x, <scalable 4 x float&...

...x float> @llvm.evl.fsub.v4f32(<scalable 4 x float> %x, <scalable 4 x float> %y, <scalable 1 x i1> %M, i32 %L) would then indicate the the mask %M applies to groups of "4 / 1" float elements. - Simon > Jacob Lifshay > > On Thu, Jan 31, 2019, 07:58 Simon Moll via llvm-dev > <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org> wrote: > > Hi, > > There is now an RFC for a roadmap to native vector predication > support in LLVM and a prototype implementation: > > https://reviews.llvm.org/D57504 &g...

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On Thu, Feb 7, 2019, 09:21 Simon Moll <moll at cs.uni-saarland.de> wrote: > > On 2/7/19 6:08 PM, David Greene wrote: > > Jacob Lifshay <programmerjake at gmail.com> writes: > > > >> So it would be handy for the vector length on evl intrinsics to be in > >> units of the mask length so we...

...lowing to move forward: -  Can we agree on EVL intrinsics as a transitional step to predicated IR instructions? -  Can we agree on native EVL SDNodes for CodeGen? -  Are the changes to InstCombine/InstSimplify/DAGCombiner and utility classes that go with it acceptable? Thanks Simon -- Simon Moll Researcher / PhD Student Compiler Design Lab (Prof. Hack) Saarland University, Computer Science Building E1.3, Room 4.31 Tel. +49 (0)681 302-57521 : moll at cs.uni-saarland.de Fax. +49 (0)681 302-3065 : http://compilers.cs.uni-saarland.de/people/moll -------------- next part -------------- An H...

Has any one had any success with cow implementation in xen ? I found this somewhere http://www.atconsultancy.nl/cowloop/, has anyone tried it out with xen ? -- regards, Anand _______________________________________________ Xen-users mailing list Xen-users@lists.xensource.com http://lists.xensource.com/xen-users

Hi Rusty, Would you be so kind and consider getting those two small fixes into 3.7 merge? All credits go to Brian, all shame on me :-) Cheers! Pawel Brian Foley (2): virtio_mmio: fix off by one error allocating queue virtio_mmio: Don't attempt to create empty virtqueues drivers/virtio/virtio_mmio.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) -- 1.7.9.5

Hi Rusty, Would you be so kind and consider getting those two small fixes into 3.7 merge? All credits go to Brian, all shame on me :-) Cheers! Pawel Brian Foley (2): virtio_mmio: fix off by one error allocating queue virtio_mmio: Don't attempt to create empty virtqueues drivers/virtio/virtio_mmio.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) -- 1.7.9.5

On 2/5/19 12:06 PM, Bruce Hoult wrote: > On Tue, Feb 5, 2019 at 1:23 AM Simon Moll <moll at cs.uni-saarland.de> wrote: >> I think this is the usual mixup of AVL and MVL. >> >> AVL: is part of the predicate and can change between vector operations >> just like a mask can (light weight). >> >> MVL: Is the physical vector register length and...

Jacob Lifshay <programmerjake at gmail.com> writes: > So it would be handy for the vector length on evl intrinsics to be in > units of the mask length so we don't have to pattern match a division > in the backend. We could have 2 variants of the vector length > argument, one in terms of the data vector and one in terms of the mask > vector. we could legalize the mask

On Mon, 4 Feb 2019 at 18:15, David Greene via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Simon Moll <moll at cs.uni-saarland.de> writes: > > > You are referring to the sub-vector sizes, if i am understanding > > correctly. I'd assume that the mask sub-vector length always has to be > > either 1 or the same as the data sub-vector length. For example, this > > i...

...ic get.active.mask to a target specific one. All predication remains explicit, and this remains the case. Only at the end, we use this intrinsic to instruction select a specific variant of the hardwarloop with some implicit predication. Cheers, Sjoerd. ________________________________ From: Simon Moll <Simon.Moll at EMEA.NEC.COM> Sent: 19 May 2020 09:56 To: Sjoerd Meijer <Sjoerd.Meijer at arm.com> Cc: Roger Ferrer Ibáñez <rofirrim at gmail.com>; Eli Friedman <efriedma at quicinc.com>; listmail at philipreames.com <listmail at philipreames.com>; llvm-dev <llvm-dev...

...nd BTC the backedge taken count. This completely piggy backs on everything that is already there in the vectoriser, and nothing is fundamentally changed here. Now, this seems very generic, and doesn't seem to bite the VP intrinsics. Cheers, Sjoerd. ________________________________ From: Simon Moll <Simon.Moll at EMEA.NEC.COM> Sent: 19 May 2020 15:07 To: Sjoerd Meijer <Sjoerd.Meijer at arm.com> Cc: Roger Ferrer Ibáñez <rofirrim at gmail.com>; Eli Friedman <efriedma at quicinc.com>; listmail at philipreames.com <listmail at philipreames.com>; llvm-dev <llvm-dev...

...t of the scalar loop explicit. I will look again, but I don't think the VP intrinsics were able to provide this. But to be honest, I have no preference at all what this intrinsic is, it is not relevant, as long as we can make this explicit. Cheers. ________________________________ From: Simon Moll <Simon.Moll at EMEA.NEC.COM> Sent: 18 May 2020 14:11 To: Sjoerd Meijer <Sjoerd.Meijer at arm.com> Cc: Roger Ferrer Ibáñez <rofirrim at gmail.com>; Eli Friedman <efriedma at quicinc.com>; listmail at philipreames.com <listmail at philipreames.com>; llvm-dev <llvm-dev...

...That could allow easier reuse by other frontends. Get Outlook for Android<https://aka.ms/ghei36> ________________________________ From: Tian, Xinmin <xinmin.tian at intel.com> Sent: Monday, June 24, 2019 5:28:45 PM To: Saito, Hideki; Francesco Petrogalli; Doerfert, Johannes Cc: Simon Moll; LLVM Development List; Clang Dev; Renato Golin; Finkel, Hal J.; Andrea Bocci; Elovikov, Andrei; Alexey Bataev; nd; Roman Lebedev; Philip Reames; Shawn Landden Subject: RE: RFC: Interface user provided vector functions with the vectorizer. >>>>I don’t know if this is going to be a prob...

...2015-03-30 at 18:37 +0100, Michael S. Tsirkin wrote: > virtio_device_is_legacy_only is always false now, > drop the test from virtio mmio. > > Signed-off-by: Michael S. Tsirkin <mst at redhat.com> Slightly ironic ack ;-) after all the battle you fought for this: Acked-by: Pawel Moll <pawel.moll at arm.com> Thanks! Pawel

...2015-03-30 at 18:37 +0100, Michael S. Tsirkin wrote: > virtio_device_is_legacy_only is always false now, > drop the test from virtio mmio. > > Signed-off-by: Michael S. Tsirkin <mst at redhat.com> Slightly ironic ack ;-) after all the battle you fought for this: Acked-by: Pawel Moll <pawel.moll at arm.com> Thanks! Pawel

...rd node; - set the machine compatible to "xen,xenvm-4.2", "xen,xenvm"; - rename the dts file to xenvm-4.2.dts; - add "xen,xenvm" to the list of compatible DT strings to mach-vexpress. Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> CC: Pawel Moll <pawel.moll@arm.com> CC: Arnd Bergmann <arnd@arndb.de> --- arch/arm/boot/dts/xenvm-4.2.dts | 64 ++++++++++++++++++++++++++++++++++ arch/arm/mach-vexpress/Makefile.boot | 3 +- arch/arm/mach-vexpress/v2m.c | 1 + 3 files changed, 67 insertions(+), 1 deletions(-) c...

On Mon, 4 Feb 2019 at 22:04, Simon Moll <moll at cs.uni-saarland.de> wrote: > On 2/4/19 9:18 PM, Robin Kruppe wrote: > > > > On Mon, 4 Feb 2019 at 18:15, David Greene via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > >> Simon Moll <moll at cs.uni-saarland.de> writes: >> >> &gt...

Adam Nemet via llvm-dev <llvm-dev at lists.llvm.org> writes: > I spent some time chatting with Adam about this and have a better > understanding of his concerns here. It seems to me that if having > masking intrinsics is the long-term solution we want, we should do > that now (for add and sub) rather than building arbitrary matrix > layout info into