Displaying 10 results from an estimated 10 matches for "mo_immedi".
2011 Mar 03
2
[LLVMdev] MachineOperand type
Hi all,
I have a question about the types of MachineOperand. There are 12
different types of MachineOperand such as MO_Register, MO_Immediate and
so on. Some of the names are self-explanatory such as MO_Register and
MO_Immediate. Some of them are a little confusing such as MO_FrameIndex,
MO_ConstantPoolIndex and so on. For example, what is the different
between MO_ExternalSymbol and MO_GlobalAddress? Are these two types
orthogona...
2009 Jan 23
1
[LLVMdev] How to determine Immediate Type in MachineOperand class?
Hi,
I would like to get the type of immediate value (integer) from MachineOperand Class. Currently the immediate value is being represented as int64_t.
int64_t ImmVal; // For MO_Immediate.
Is it possible to find out whether the immediate value is int8, 16, 32 etc?
Note: My target has a virtual Instruction set.
Thanks in advance,
-Sanjay
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2009 May 06
0
[LLVMdev] Question on tablegen
...to do this is to handle this in the AsmPrinter, with
operand modifiers.
For example, on x86 there are instructions with ${dst:call} in
their asm string. The "call" part is interpreted as an operand
modifier. The assembly printer looks for the "call" modifier
on MachineOperand::MO_Immediate operands
(in X86ATTAsmPrinter::printOperand), which lets it perform custom
printing for that type of operand. You could use a modifier which
tells the AsmPrinter to print an immediate as the appropriate
letter.
Dan
On May 5, 2009, at 10:23 PM, Manjunath Kudlur wrote:
> Hello,
>
> I...
2009 May 06
2
[LLVMdev] Question on tablegen
Hello,
I am trying to create a machine instruction for "extractelement". I
want to translate
r <- extractelement v, 0
to
mov r, v.x
I was looking at the dag I can use and I found vector_extract. The
inputs for this SDnode are a register and a iPtr constant. With that,
I need to create 4 separate def's to extract element 0, 1, 2, and 3
and translate to v.x, v.y, v.z, and v.w. I
2009 May 08
2
[LLVMdev] Question on tablegen
...in the AsmPrinter, with
> operand modifiers.
>
> For example, on x86 there are instructions with ${dst:call} in
> their asm string. The "call" part is interpreted as an operand
> modifier. The assembly printer looks for the "call" modifier
> on MachineOperand::MO_Immediate operands
> (in X86ATTAsmPrinter::printOperand), which lets it perform custom
> printing for that type of operand. You could use a modifier which
> tells the AsmPrinter to print an immediate as the appropriate
> letter.
>
> Dan
>
>
> On May 5, 2009, at 10:23 PM, Manjuna...
2009 May 08
0
[LLVMdev] Question on tablegen
...in the AsmPrinter, with
> operand modifiers.
>
> For example, on x86 there are instructions with ${dst:call} in
> their asm string. The "call" part is interpreted as an operand
> modifier. The assembly printer looks for the "call" modifier
> on MachineOperand::MO_Immediate operands
> (in X86ATTAsmPrinter::printOperand), which lets it perform custom
> printing for that type of operand. You could use a modifier which
> tells the AsmPrinter to print an immediate as the appropriate
> letter.
>
> Dan
>
>
> On May 5, 2009, at 10:23 PM, Manjuna...
2012 Oct 29
3
[LLVMdev] [llvm-commits] [llvm] r162770 - in /llvm/trunk: include/llvm/CodeGen/MachineOperand.h lib/CodeGen/MachineInstr.cpp
...mbine(MO.getType(), MO.getTargetFlags(),
> MO.getReg(),
> - MO.getSubReg(), MO.isDef());
> + // Register operands don't have target flags.
> + return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(),
> + MO.isDef());
> case MachineOperand::MO_Immediate:
> return hash_combine(MO.getType(), MO.getTargetFlags(),
> MO.getImm());
> case MachineOperand::MO_CImmediate:
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/...
2012 Oct 29
0
[LLVMdev] [llvm-commits] [llvm] r162770 - in /llvm/trunk: include/llvm/CodeGen/MachineOperand.h lib/CodeGen/MachineInstr.cpp
...etTargetFlags(),
>> MO.getReg(),
>> - MO.getSubReg(), MO.isDef());
>> + // Register operands don't have target flags.
>> + return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(),
>> + MO.isDef());
>> case MachineOperand::MO_Immediate:
>> return hash_combine(MO.getType(), MO.getTargetFlags(),
>> MO.getImm());
>> case MachineOperand::MO_CImmediate:
>>
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>>...
2012 Oct 29
2
[LLVMdev] [llvm-commits] [llvm] r162770 - in /llvm/trunk: include/llvm/CodeGen/MachineOperand.h lib/CodeGen/MachineInstr.cpp
...MO.getReg(),
> >> - MO.getSubReg(), MO.isDef());
> >> + // Register operands don't have target flags.
> >> + return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(),
> >> + MO.isDef());
> >> case MachineOperand::MO_Immediate:
> >> return hash_combine(MO.getType(), MO.getTargetFlags(),
> >> MO.getImm());
> >> case MachineOperand::MO_CImmediate:
> >>
> >>
> >> _______________________________________________
> >> llvm-commits mailing list
> >&...
2013 Dec 05
3
[LLVMdev] X86 - Help on fixing a poor code generation bug
...ntInsertsPass() {
+ return new X86FoldRedundantInserts();
+}
+
+bool X86FoldRedundantInserts::isValidINSERTPS(const MachineInstr &MI) const {
+ const MachineOperand &Op2 = MI.getOperand(2);
+ const MachineOperand &Op3 = MI.getOperand(3);
+
+ return ((Op3.getType() == MachineOperand::MO_Immediate) &&
+ (Op3.getImm() == 0) &&
+ (Op2.isKill() && !MRI->isReserved(Op2.getReg())));
+}
+
+bool X86FoldRedundantInserts::isValidMOVSS(const MachineInstr &MI) const {
+ const MachineOperand &MO = MI.getOperand(2);
+ unsigned Reg = MO.getReg();
+...