Displaying 15 results from an estimated 15 matches for "mo1".
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m1
2010 Oct 18
1
Question about lme (mixed effects regression)
...age + Sex| Subject)
If I run:
summary(fm1)
then I can see the fixed effects for age and sex (17.7 for intercept,
0.66 for age, and -1.66 for SexFemale)
If I run:
ranef(fm1)
Then it looks like it's producing the random effects for each subgroup
(in this example - each subject). For example, for MO1 it's:
1.25 for intercept, 0.106 for age, and -1.52 for SexFemale.
So, in order to get the the total effects, i.e., the regression
equation, for each subgroup (Subject) I need to do this:
For example, for Subject MO1:
y(M01) = (17.71+1.25)+(0.66+0.106)*Age+(-1.66-1.52)*SexFemale = 18.96
+ 0.766...
2008 Apr 16
0
[LLVMdev] Being able to know the jitted code-size before emitting
...Imm(), sizeOfImm(Desc));
> + emitConstant(MO.getImm(), X86InstrInfo::sizeOfImm(Desc));
> } else {
> assert(0 && "Unknown RawFrm operand!");
> }
> @@ -669,7 +534,7 @@
>
> if (CurOp != NumOps) {
> const MachineOperand &MO1 = MI.getOperand(CurOp++);
> - unsigned Size = sizeOfImm(Desc);
> + unsigned Size = X86InstrInfo::sizeOfImm(Desc);
> if (MO1.isImmediate())
> emitConstant(MO1.getImm(), Size);
> else {
> @@ -698,7 +563,7 @@
> getX86RegNum(MI.get...
2008 Apr 15
4
[LLVMdev] Being able to know the jitted code-size before emitting
OK, here's a new patch that adds the infrastructure and the
implementation for X86, ARM and PPC of GetInstSize and GetFunctionSize.
Both functions are virtual functions defined in TargetInstrInfo.h.
For X86, I moved some commodity functions from X86CodeEmitter to
X86InstrInfo.
What do you think?
Nicolas
Evan Cheng wrote:
>
> I think both of these belong to TargetInstrInfo. And
2011 Jun 22
0
[LLVMdev] ARM thumb-2 instruction used for non-thumb2 CPUs
...tr(ARM_AM::getSORegShOp(MO3.getImm()));
+ O << '\t' << "mov";
printSBitModifierOperand(MI, 6, O);
printPredicateOperand(MI, 4, O);
O << '\t' << getRegisterName(Dst.getReg())
- << ", " << getRegisterName(MO1.getReg());
+ << ", " << getRegisterName(MO1.getReg())
+ << ", " << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));;
if (ARM_AM::getSORegShOp(MO3.getImm()) == ARM_AM::rrx)
return;
- O << ", ";
+ O...
2011 Jun 22
2
[LLVMdev] ARM thumb-2 instruction used for non-thumb2 CPUs
On Jun 22, 2011, at 9:00 AM, Renato Golin wrote:
> On 22 June 2011 16:50, Jim Grosbach <grosbach at apple.com> wrote:
>>> This sounds like a dead end as newer binutils are GPLv3.
>>
>> Yeah, that's definitely a very real concern and a big motivation to get the MC based asm parser whipped into usable shape. We're much more in control of our own destiny then.
2011 Jun 22
2
[LLVMdev] ARM thumb-2 instruction used for non-thumb2 CPUs
...3.getImm()));
> + O << '\t' << "mov";
> printSBitModifierOperand(MI, 6, O);
> printPredicateOperand(MI, 4, O);
>
> O << '\t' << getRegisterName(Dst.getReg())
> - << ", " << getRegisterName(MO1.getReg());
> + << ", " << getRegisterName(MO1.getReg())
> + << ", " << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));;
>
> if (ARM_AM::getSORegShOp(MO3.getImm()) == ARM_AM::rrx)
> return;
>
> - O...
2015 Dec 14
2
Tablegen definition question
Hi,
That's what the DecoderMethod is for. Similarly ParserMatchClass for the
asm parser and PrintMethod for the asm printer:
def CondCodeOperand : AsmOperandClass { let Name = "CondCode"; }
def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm),
(ops (i32 14), (i32 zero_reg))> {
let PrintMethod = "printPredicateOperand";
2016 Aug 01
2
OpenSSH 7.3p1 can't be build on Solaris 10
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA256
The same result without CFLAGS:
configure:17300: checking for mblen
configure:17356: gcc -o conftest -g -O2 -Wall -Wpointer-arith
-Wuninitialized -Wsign-compare -Wformat-security
-Wsizeof-pointer-memaccess -Wno-pointer-sign -Wno-unused-result
-fno-strict-aliasing -D_FORTIFY_SOURCE=2 -ftrapv -fno-builtin-memset
-fstack-protector-strong -fPIE
2009 Jun 03
5
[LLVMdev] patch for llc/ARM: added mechanism to move switch tables from .text -> .data; also cleanup and documentation
...uot;)";
if (ACPV->getPCAdjustment() != 0) {
O << "-(" << TAI->getPrivateGlobalPrefix() << "PC"
@@ -695,12 +707,31 @@
}
}
+
void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNo) {
- const MachineOperand &MO1 = MI->getOperand(OpNo);
- const MachineOperand &MO2 = MI->getOperand(OpNo+1); // Unique Id
- unsigned JTI = MO1.getIndex();
- O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
- << '_' << JTI << '_' &l...
2009 Jun 11
0
[LLVMdev] patch for llc/ARM: added mechanism to move switch tables from .text -> .data; also cleanup and documentation
On Jun 8, 2009, at 2:42 PM, robert muth wrote:
> On Sun, Jun 7, 2009 at 11:53 PM, Evan Cheng <evan.cheng at apple.com>
> wrote:
>>
>> On Jun 7, 2009, at 6:59 AM, robert muth wrote:
>>
>>> On Sat, Jun 6, 2009 at 4:51 PM, Evan Cheng<evan.cheng at apple.com>
>>> wrote:
>>>> +cl::opt<std::string>
2009 Jun 08
2
[LLVMdev] patch for llc/ARM: added mechanism to move switch tables from .text -> .data; also cleanup and documentation
On Sun, Jun 7, 2009 at 11:53 PM, Evan Cheng <evan.cheng at apple.com> wrote:
>
> On Jun 7, 2009, at 6:59 AM, robert muth wrote:
>
>> On Sat, Jun 6, 2009 at 4:51 PM, Evan Cheng<evan.cheng at apple.com>
>> wrote:
>>> +cl::opt<std::string> FlagJumpTableSection("jumptable-section",
>>> +
2016 Nov 09
0
[PATCH] filearch: Add s390 and s390x detection and tests.
...HGCC^>iG;v!CuCvi$EX=W#OkKO=H}jymj_h$5Z%xtW<yyQ4U<o^mJB<LNW*
zc;?JR=7}>C?&xwM@6P*y!B3B$>f|ECF-hJ}a!xlQ;Jhy3x@!S&j!U@Sg7f)1+!un&
ze$nwY-nA1tYoM5QF>Q@U*Vkw%*{|U~5IpW2O@rip*dzNx^m#vq_bq~d_<RZp{K)&X
ztrfWfK4hBVd!<?6A7NbHC&5#UXACtp^zUVSGJ?}t66NrIfxev6jhJiTa!#MO1;CHn
zJhz>MY8}MjXR#UL#+k)th>P2_g>PE^E?IcP!aooH(Q(rLdjVBk+-|h}$nT=|_5<k0
z#sBRN^ZF<BW7g3*20U)QI5@|}$2kH0nDufVbwYi6y`0CPFY9Hki!<5QcdhU^OOIGw
zyXmakS{A;I!N>Xk1~yO3es;dq!OyGkBkOX(^8Y;xx5xi_2R}dUfd2vG`S5!>wo$K*
z;X-C?ZFP05e)fsX=IL4?zwQU8OU25@=9vC<8(XafIb7mYE~cxvta*B7*;`z=xPtql...
2009 Jun 24
2
[LLVMdev] patch for llc/ARM: added mechanism to move switch tables from .text -> .data; also cleanup and documentation
...uot;)";
if (ACPV->getPCAdjustment() != 0) {
O << "-(" << TAI->getPrivateGlobalPrefix() << "PC"
@@ -757,12 +767,31 @@
}
}
+
void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNo) {
- const MachineOperand &MO1 = MI->getOperand(OpNo);
- const MachineOperand &MO2 = MI->getOperand(OpNo+1); // Unique Id
- unsigned JTI = MO1.getIndex();
- O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
- << '_' << JTI << '_' &l...
2016 Aug 02
6
OpenSSH 7.3p1 can't be build on Solaris 10
...ter support.
> AC_CHECK_FUNCS([mblen mbtowc nl_langinfo wcwidth])
> -CFLAGS="$saved_CFLAGS"
>
> AC_LINK_IFELSE(
> [AC_LANG_PROGRAM(
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nz/7mzLYAvM8/iGOEnmXlz122qB0hx16n9JX3aIxUTEDjaz6LXIEaO/NAm...
2012 Apr 19
0
[LLVMdev] Target Dependent Hexagon Packetizer patch
...OpNo, raw_ostream&O) const {
>> +void HexagonInstPrinter::printMEMriOperand(const MCInst *MI, unsigned OpNo,
>> + raw_ostream&O) const {
>> const MCOperand& MO0 = MI->getOperand(OpNo);
>> const MCOperand& MO1 = MI->getOperand(OpNo + 1);
>>
>> @@ -103,8 +134,8 @@ void HexagonInstPrinter::printMEMriOperand
>> O<< " + #"<< MO1.getImm();
>> }
>>
>> -void HexagonInstPrinter::printFrameIndexOperand
>> - (const MCInst *MI, unsigned OpN...