Displaying 7 results from an estimated 7 matches for "mmword".
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xmmword
2013 Jul 19
0
[LLVMdev] llvm.x86.sse2.sqrt.pd not using sqrtpd, calling a function that modifies ECX
...--------------
002E00D0 push ebp
002E00D1 mov ebp,esp
002E00D3 push ebx
002E00D4 push edi
002E00D5 push esi
002E00D6 and esp,0FFFFFFF0h
002E00DC sub esp,110h
002E00E2 mov eax,dword ptr [ebp+8]
002E00E5 movddup xmm0,mmword ptr [eax+10h]
002E00EA movapd xmmword ptr [esp+80h],xmm0
002E00F3 movddup xmm0,mmword ptr [eax+8]
002E00F8 movapd xmmword ptr [esp+70h],xmm0
002E00FE movddup xmm0,mmword ptr [eax]
002E0102 movapd xmmword ptr [esp+60h],xmm0
002E0108 xorpd xmm0,xmm0
002E010C...
2013 Jul 19
4
[LLVMdev] SIMD instructions and memory alignment on X86
Hmm, I'm not able to get those .ll files to compile if I disable SSE and I
end up with SSE instructions(including sqrtpd) if I don't disable it.
On Thu, Jul 18, 2013 at 10:53 PM, Peter Newman <peter at uformia.com> wrote:
> Is there something specifically required to enable SSE? If it's not
> detected as available (based from the target triple?) then I don't think
2011 Oct 26
2
[LLVMdev] Lowering to MMX
...eclare x86_mmx @llvm.x86.mmx.punpcklbw(x86_mmx, x86_mmx) nounwind readnone
Which gives me the following assembly code:
push ebp
mov ebp,esp
and esp,0FFFFFFF0h
sub esp,20h
mov eax,dword ptr [ebp+0Ch]
movd xmm0,dword ptr [eax]
movapd xmmword ptr [esp],xmm0
movq mm0,mmword ptr [esp]
punpcklbw mm0,mm0
mov eax,dword ptr [ebp+8]
movq mmword ptr [eax],mm0
emms
mov esp,ebp
pop ebp
ret
The inner portion could look like this instead:
movd mm0,dword ptr [eax]
punpcklbw mm0,m...
2011 Oct 26
0
[LLVMdev] Lowering to MMX
...bw(x86_mmx, x86_mmx) nounwind readnone
>
> Which gives me the following assembly code:
>
> push ebp
> mov ebp,esp
> and esp,0FFFFFFF0h
> sub esp,20h
> mov eax,dword ptr [ebp+0Ch]
> movd xmm0,dword ptr [eax]
> movapd xmmword ptr [esp],xmm0
> movq mm0,mmword ptr [esp]
> punpcklbw mm0,mm0
> mov eax,dword ptr [ebp+8]
> movq mmword ptr [eax],mm0
> emms
> mov esp,ebp
> pop ebp
> ret
>
> The inner portion could look like this instead:
>
> movd...
2011 Oct 25
0
[LLVMdev] Lowering to MMX
On Oct 20, 2011, at 8:42 AM, Nicolas Capens wrote:
> Hi all,
>
> I'm working on a graphics project which uses LLVM for dynamic code
> generation, and I noticed a major performance regression when upgrading
> from LLVM 2.8 to 3.0-rc1 (LLVM 2.9 didn't support Win64 so I skipped it
> entirely).
>
> I found out that the performance regression is due to removing
2011 Oct 20
4
[LLVMdev] Lowering to MMX
Hi all,
I'm working on a graphics project which uses LLVM for dynamic code
generation, and I noticed a major performance regression when upgrading
from LLVM 2.8 to 3.0-rc1 (LLVM 2.9 didn't support Win64 so I skipped it
entirely).
I found out that the performance regression is due to removing support
for lowering 64-bit vector operations to MMX, and using SSE2 instead. My
code uses a
2009 Jul 09
2
[LLVMdev] Wrong encoding of movd on x64
...%7 = bitcast i8* %1 to i32* ; <i32*> [#uses=1]
store i32 %6, i32* %7, align 1
ret void
}
It generates the following code:
mov rax,1E417A8h
mov rax,qword ptr [rax]
mov rcx,1E417B0h
mov rcx,qword ptr [rcx]
movq mm0,mmword ptr [rcx]
movq rax,mm1
mov dword ptr [rax],ecx
Note the last movq. What was probably intended to be generated was "movd
ecx, mm0". LLVM mistakenly sets the 'wide' bit of the REX prefix to 1,
turning movd into movq. Also, reg and r/m encoding has been swappe...