Displaying 20 results from an estimated 23 matches for "mkop1".
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mkop2
2014 May 21
2
[Mesa-dev] [PATCH 04/12] nv50/ir/tgsi: TGSI_OPCODE_POW replicates its result
...DE_OR:
> - case TGSI_OPCODE_POW:
> case TGSI_OPCODE_SHL:
> case TGSI_OPCODE_ISHR:
> case TGSI_OPCODE_USHR:
> @@ -2254,6 +2253,11 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
> FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
> mkOp1(OP_MOV, TYPE_U32, dst0[c], fetchSrc(0, c));
> break;
> + case TGSI_OPCODE_POW:
> + val0 = mkOp2v(op, TYPE_F32, getScratch(), fetchSrc(0, 0), fetchSrc(1, 0));
> + FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
> + mkOp1(OP_MOV, TYPE_F32, dst0[c], val0);
> +...
2014 May 21
2
[Mesa-dev] [PATCH 04/12] nv50/ir/tgsi: TGSI_OPCODE_POW replicates its result
...t; case TGSI_OPCODE_SHL:
>>> case TGSI_OPCODE_ISHR:
>>> case TGSI_OPCODE_USHR:
>>> @@ -2254,6 +2253,11 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
>>> FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
>>> mkOp1(OP_MOV, TYPE_U32, dst0[c], fetchSrc(0, c));
>>> break;
>>> + case TGSI_OPCODE_POW:
>>> + val0 = mkOp2v(op, TYPE_F32, getScratch(), fetchSrc(0, 0), fetchSrc(1, 0));
>>> + FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
>>> + mkOp1(OP_M...
2014 Nov 18
2
[PATCH] nv50/ir: saturate FRC result to avoid completely bogus values
...0644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -2512,7 +2512,8 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
src0 = fetchSrc(0, c);
val0 = getScratch();
mkOp1(OP_FLOOR, TYPE_F32, val0, src0);
- mkOp2(OP_SUB, TYPE_F32, dst0[c], src0, val0);
+ mkOp2(OP_SUB, TYPE_F32, val0, src0, val0);
+ mkOp1(OP_SAT, TYPE_F32, dst0[c], val0);
}
break;
case TGSI_OPCODE_ROUND:
--
2.0.4
2015 Feb 20
10
[PATCH 01/11] nvc0/ir: add emission of dadd/dmul/dmad opcodes, fix minmax
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
.../drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 66 +++++++++++++++++++++-
1 file changed, 63 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
index dfb093c..e38a3b8 100644
---
2014 Nov 18
2
[Mesa-dev] [PATCH] nv50/ir: saturate FRC result to avoid completely bogus values
...n/nv50_ir_from_tgsi.cpp
>> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
>> @@ -2512,7 +2512,8 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
>> src0 = fetchSrc(0, c);
>> val0 = getScratch();
>> mkOp1(OP_FLOOR, TYPE_F32, val0, src0);
>> - mkOp2(OP_SUB, TYPE_F32, dst0[c], src0, val0);
>> + mkOp2(OP_SUB, TYPE_F32, val0, src0, val0);
>> + mkOp1(OP_SAT, TYPE_F32, dst0[c], val0);
>> }
>> break;
>> case TGSI_OPCODE_ROUND:
&g...
2014 May 20
0
[PATCH 04/12] nv50/ir/tgsi: TGSI_OPCODE_POW replicates its result
..._OPCODE_UMUL_HI:
case TGSI_OPCODE_OR:
- case TGSI_OPCODE_POW:
case TGSI_OPCODE_SHL:
case TGSI_OPCODE_ISHR:
case TGSI_OPCODE_USHR:
@@ -2254,6 +2253,11 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
mkOp1(OP_MOV, TYPE_U32, dst0[c], fetchSrc(0, c));
break;
+ case TGSI_OPCODE_POW:
+ val0 = mkOp2v(op, TYPE_F32, getScratch(), fetchSrc(0, 0), fetchSrc(1, 0));
+ FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
+ mkOp1(OP_MOV, TYPE_F32, dst0[c], val0);
+ break;
case TGSI_OPCODE_...
2014 May 21
0
[Mesa-dev] [PATCH 04/12] nv50/ir/tgsi: TGSI_OPCODE_POW replicates its result
...ODE_SHL:
>>>> case TGSI_OPCODE_ISHR:
>>>> case TGSI_OPCODE_USHR:
>>>> @@ -2254,6 +2253,11 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
>>>> FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
>>>> mkOp1(OP_MOV, TYPE_U32, dst0[c], fetchSrc(0, c));
>>>> break;
>>>> + case TGSI_OPCODE_POW:
>>>> + val0 = mkOp2v(op, TYPE_F32, getScratch(), fetchSrc(0, 0), fetchSrc(1, 0));
>>>> + FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
>>>>...
2014 Nov 18
1
[Mesa-dev] [PATCH] nv50/ir: saturate FRC result to avoid completely bogus values
...+ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
>>>> @@ -2512,7 +2512,8 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
>>>> src0 = fetchSrc(0, c);
>>>> val0 = getScratch();
>>>> mkOp1(OP_FLOOR, TYPE_F32, val0, src0);
>>>> - mkOp2(OP_SUB, TYPE_F32, dst0[c], src0, val0);
>>>> + mkOp2(OP_SUB, TYPE_F32, val0, src0, val0);
>>>> + mkOp1(OP_SAT, TYPE_F32, dst0[c], val0);
>>>> }
>>>> brea...
2014 Jun 23
1
[PATCH] nv50/ir: make ARB_viewport_array behave like it does with other drivers
...if (ptr || (info->out[idx].mask & (1 << c))) {
+ /* Save the viewport index into a scratch register so that it can be
+ exported at EMIT time */
+ if (info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_VIEWPORT_INDEX && viewport != NULL)
+ mkOp1(OP_MOV, TYPE_U32, viewport, val);
+ else
+ mkStore(OP_EXPORT, TYPE_U32, dstToSym(dst, c), ptr, val);
+ }
} else
if (f == TGSI_FILE_TEMPORARY ||
f == TGSI_FILE_PREDICATE ||
@@ -2523,6 +2535,14 @@ Converter::handleInstruction(const struct tgsi_full_instruction...
2014 May 18
1
[PATCH 1/2] nv50/ir: fix s32 x s32 -> high s32 multiply logic
...ue *c[2];
Value *t[4];
for (int j = 0; j < 4; ++j)
t[j] = bld->getSSA(fullSize);
+ s[0] = mul->getSrc(0);
+ s[1] = mul->getSrc(1);
+
+ if (isSignedType(mul->sType)) {
+ s[0] = bld->getSSA(fullSize);
+ s[1] = bld->getSSA(fullSize);
+ bld->mkOp1(OP_ABS, mul->sType, s[0], mul->getSrc(0));
+ bld->mkOp1(OP_ABS, mul->sType, s[1], mul->getSrc(1));
+ }
+
// split sources into halves
- i[0] = bld->mkSplit(a, halfSize, mul->getSrc(0));
- i[1] = bld->mkSplit(b, halfSize, mul->getSrc(1));
+ i[0] = bld->...
2014 Jun 23
1
[PATCH v3] nv50/ir: make ARB_viewport_array behave like it does with other drivers
...if (ptr || (info->out[idx].mask & (1 << c))) {
+ /* Save the viewport index into a scratch register so that it can be
+ exported at EMIT time */
+ if (info->out[idx].sn == TGSI_SEMANTIC_VIEWPORT_INDEX
+ && viewport != NULL)
+ mkOp1(OP_MOV, TYPE_U32, viewport, val);
+ else
+ mkStore(OP_EXPORT, TYPE_U32, dstToSym(dst, c), ptr, val);
+ }
} else
if (f == TGSI_FILE_TEMPORARY ||
f == TGSI_FILE_PREDICATE ||
@@ -2523,6 +2538,13 @@ Converter::handleInstruction(const struct tgsi_full_instruction...
2014 Jun 23
1
[PATCH v2] nv50/ir: make ARB_viewport_array behave like it does with other drivers
...if (ptr || (info->out[idx].mask & (1 << c))) {
+ /* Save the viewport index into a scratch register so that it can be
+ exported at EMIT time */
+ if (info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_VIEWPORT_INDEX && viewport != NULL)
+ mkOp1(OP_MOV, TYPE_U32, viewport, val);
+ else
+ mkStore(OP_EXPORT, TYPE_U32, dstToSym(dst, c), ptr, val);
+ }
} else
if (f == TGSI_FILE_TEMPORARY ||
f == TGSI_FILE_PREDICATE ||
@@ -2523,6 +2537,14 @@ Converter::handleInstruction(const struct tgsi_full_instruction...
2014 May 21
0
[Mesa-dev] [PATCH 04/12] nv50/ir/tgsi: TGSI_OPCODE_POW replicates its result
...I_OPCODE_POW:
>> case TGSI_OPCODE_SHL:
>> case TGSI_OPCODE_ISHR:
>> case TGSI_OPCODE_USHR:
>> @@ -2254,6 +2253,11 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
>> FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
>> mkOp1(OP_MOV, TYPE_U32, dst0[c], fetchSrc(0, c));
>> break;
>> + case TGSI_OPCODE_POW:
>> + val0 = mkOp2v(op, TYPE_F32, getScratch(), fetchSrc(0, 0), fetchSrc(1, 0));
>> + FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
>> + mkOp1(OP_MOV, TYPE_F32, dst0[c...
2014 Sep 26
0
[PATCH] gm107/ir: take relative pfetch offset into account
.../codegen/nv50_ir_lowering_gm107.cpp
@@ -159,7 +159,10 @@ GM107LoweringPass::handlePFETCH(Instruction *i)
bld.mkOp2(OP_SHR , TYPE_U32, tmp1, tmp0, bld.mkImm(16));
bld.mkOp2(OP_AND , TYPE_U32, tmp0, tmp0, bld.mkImm(0xff));
bld.mkOp2(OP_AND , TYPE_U32, tmp1, tmp1, bld.mkImm(0xff));
- bld.mkOp1(OP_MOV , TYPE_U32, tmp2, bld.mkImm(i->getSrc(0)->reg.data.u32));
+ if (i->getSrc(1))
+ bld.mkOp2(OP_ADD , TYPE_U32, tmp2, i->getSrc(0), i->getSrc(1));
+ else
+ bld.mkOp1(OP_MOV , TYPE_U32, tmp2, i->getSrc(0));
bld.mkOp3(OP_MAD , TYPE_U32, tmp0, tmp0, tmp1, tmp2);...
2014 Nov 18
0
[Mesa-dev] [PATCH] nv50/ir: saturate FRC result to avoid completely bogus values
...ivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
> @@ -2512,7 +2512,8 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
> src0 = fetchSrc(0, c);
> val0 = getScratch();
> mkOp1(OP_FLOOR, TYPE_F32, val0, src0);
> - mkOp2(OP_SUB, TYPE_F32, dst0[c], src0, val0);
> + mkOp2(OP_SUB, TYPE_F32, val0, src0, val0);
> + mkOp1(OP_SAT, TYPE_F32, dst0[c], val0);
> }
> break;
> case TGSI_OPCODE_ROUND:
>
I don't underst...
2014 Nov 18
0
[Mesa-dev] [PATCH] nv50/ir: saturate FRC result to avoid completely bogus values
...cpp
>>> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
>>> @@ -2512,7 +2512,8 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
>>> src0 = fetchSrc(0, c);
>>> val0 = getScratch();
>>> mkOp1(OP_FLOOR, TYPE_F32, val0, src0);
>>> - mkOp2(OP_SUB, TYPE_F32, dst0[c], src0, val0);
>>> + mkOp2(OP_SUB, TYPE_F32, val0, src0, val0);
>>> + mkOp1(OP_SAT, TYPE_F32, dst0[c], val0);
>>> }
>>> break;
>>> ca...
2015 Jan 05
0
[PATCH] nv50/ir: change the way float face is returned
...R_INTERP_FLAT, def, addr, NULL);
if (i->dType == TYPE_F32) {
- bld.mkOp2(OP_AND, TYPE_U32, def, def, bld.mkImm(0x80000000));
- bld.mkOp2(OP_XOR, TYPE_U32, def, def, bld.mkImm(0xbf800000));
+ bld.mkOp2(OP_OR, TYPE_U32, def, def, bld.mkImm(0x00000001));
+ bld.mkOp1(OP_NEG, TYPE_S32, def, def);
+ bld.mkCvt(OP_CVT, TYPE_F32, def, TYPE_S32, def);
}
break;
case SV_NCTAID:
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index ff48e94..04cd19e 100644...
2014 May 20
14
[PATCH 00/12] Cherry-pick nv50/nvc0 patches from gallium-nine
I went through the gallium-nine tree and picked out nouveau patches that are
general bug-fixes. The first bunch I'd like to also get into 10.2. I've
reviewed all of them and they make sense to me, but sending them out for
public review as well in case there are any objections.
Unless I hear objections, I'd like to push this by Friday.
Christoph Bumiller (11):
nv50,nvc0: always pull
2015 Feb 23
2
[PATCH 1/2] nv50/ir: add fp64 support on G200 (NVA0)
...As a first guess, we use the "quake" style
+ * approximation for RSQ:
+ *
+ * 0x5fe6eb50c7b537a9 - num >> 1
+ *
+ * For RCP, we will then square it.
+ */
+ Value *abs, *guess, *parts[2], *input[2], *shr[4], *pred;
+
+ bld.setPosition(i, false);
+
+ abs = bld.mkOp1v(OP_ABS, TYPE_F64, bld.getSSA(8), i->getSrc(0));
+
+ parts[0] = bld.loadImm(NULL, 0xc7b537a9);
+ parts[1] = bld.loadImm(NULL, 0x5fe6eb50);
+ guess = bld.mkOp2v(OP_MERGE, TYPE_F64, bld.getSSA(8), parts[0], parts[1]);
+
+ bld.mkSplit(input, 4, abs);
+ shr[0] = bld.mkOp2v(OP_SHR, TYPE_U32...
2014 Feb 28
0
[PATCH] nv50: enable texture query lod
...struction *i)
{
if (i->dType == TYPE_F32) {
@@ -1196,6 +1217,8 @@ NV50LoweringPreSSA::visit(Instruction *i)
return handleTXL(i->asTex());
case OP_TXD:
return handleTXD(i->asTex());
+ case OP_TXLQ:
+ return handleTXLQ(i->asTex());
case OP_EX2:
bld.mkOp1(OP_PREEX2, TYPE_F32, i->getDef(0), i->getSrc(0));
i->setSrc(0, i->getDef(0));
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
index ae42d03..4093bc0 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir...