Displaying 20 results from an estimated 35 matches for "mkmov".
2014 May 21
2
[Mesa-dev] [PATCH 04/12] nv50/ir/tgsi: TGSI_OPCODE_POW replicates its result
...t;> + case TGSI_OPCODE_POW:
>>> + val0 = mkOp2v(op, TYPE_F32, getScratch(), fetchSrc(0, 0), fetchSrc(1, 0));
>>> + FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
>>> + mkOp1(OP_MOV, TYPE_F32, dst0[c], val0);
>>> + break;
>> Can you use mkMov ? Pretty please :)
>
> The two are used fairly interchangeably, and a lot of the surrounding
> code uses this style (as you can see in the context lines). I'd rather
> keep it as-is.
>
IMHO using mkMov makes the code easier to read for noobs like me. There are
only two cases of...
2016 Sep 27
2
[PATCH] nv50/ir: constant fold OP_SPLIT
...shift = 16;
+ type = (i->sType == TYPE_U32) ? TYPE_U16 : TYPE_S16;
+ }
+ if (i->sType == TYPE_U16 || i->sType == TYPE_S16) {
+ shift = 8;
+ type = (i->sType == TYPE_U16) ? TYPE_U8 : TYPE_S8;
+ }
+ if (type != TYPE_NONE) {
+ bld.mkMov(i->getDef(0), bld.mkImm(imm0.reg.data.u64 >> shift), type);
+ bld.mkMov(i->getDef(1), bld.mkImm(imm0.reg.data.u64), type);
+ delete_Instruction(prog, i);
+ }
+ }
+ break;
case OP_MUL:
if (i->dType == TYPE_F32)
tryCollapseChainedMULs(i, s,...
2016 Sep 30
2
[PATCH] nv50/ir: constant fold OP_SPLIT
...t;> + if (i->sType == TYPE_U16 || i->sType == TYPE_S16) {
>> + shift = 8;
>> + type = (i->sType == TYPE_U16) ? TYPE_U8 : TYPE_S8;
>> + }
> shift = typeSizeOf(i->dType);
>
>> + if (type != TYPE_NONE) {
>> + bld.mkMov(i->getDef(0), bld.mkImm(imm0.reg.data.u64 >> shift), type);
>> + bld.mkMov(i->getDef(1), bld.mkImm(imm0.reg.data.u64), type);
> u64 val = ...u64;
> for (d = 0; i->defExists(d); ++d) {
> bld.mkMov(i->getDef(d), bld.mkImm(val & ((1 << shift) - 1))...
2014 May 21
2
[Mesa-dev] [PATCH 04/12] nv50/ir/tgsi: TGSI_OPCODE_POW replicates its result
...t0[c], fetchSrc(0, c));
> break;
> + case TGSI_OPCODE_POW:
> + val0 = mkOp2v(op, TYPE_F32, getScratch(), fetchSrc(0, 0), fetchSrc(1, 0));
> + FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
> + mkOp1(OP_MOV, TYPE_F32, dst0[c], val0);
> + break;
Can you use mkMov ? Pretty please :)
-Emil
> case TGSI_OPCODE_EX2:
> case TGSI_OPCODE_LG2:
> val0 = mkOp1(op, TYPE_F32, getScratch(), fetchSrc(0, 0))->getDef(0);
>
2016 Sep 30
0
[PATCH] nv50/ir: constant fold OP_SPLIT
..._U16 || i->sType == TYPE_S16) {
>>> + shift = 8;
>>> + type = (i->sType == TYPE_U16) ? TYPE_U8 : TYPE_S8;
>>> + }
>>
>> shift = typeSizeOf(i->dType);
>>
>>> + if (type != TYPE_NONE) {
>>> + bld.mkMov(i->getDef(0), bld.mkImm(imm0.reg.data.u64 >> shift),
>>> type);
>>> + bld.mkMov(i->getDef(1), bld.mkImm(imm0.reg.data.u64), type);
>>
>> u64 val = ...u64;
>> for (d = 0; i->defExists(d); ++d) {
>> bld.mkMov(i->getDef(d), bld.mkI...
2014 May 21
0
[Mesa-dev] [PATCH 04/12] nv50/ir/tgsi: TGSI_OPCODE_POW replicates its result
..._OPCODE_POW:
>>>> + val0 = mkOp2v(op, TYPE_F32, getScratch(), fetchSrc(0, 0), fetchSrc(1, 0));
>>>> + FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
>>>> + mkOp1(OP_MOV, TYPE_F32, dst0[c], val0);
>>>> + break;
>>> Can you use mkMov ? Pretty please :)
>>
>> The two are used fairly interchangeably, and a lot of the surrounding
>> code uses this style (as you can see in the context lines). I'd rather
>> keep it as-is.
>>
> IMHO using mkMov makes the code easier to read for noobs like me. Ther...
2016 Mar 16
2
[PATCH mesa 6/6] nouveau: codegen: Disable more old resource handling code
...d for now as reference when adding img support
> getResourceCoords(off, r, 1);
>
> if (isResourceRaw(code, r)) {
> @@ -2363,6 +2371,7 @@ Converter::handleLOAD(Value *dst0[4])
> FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
> if (dst0[c] != def[c])
> mkMov(dst0[c], def[tgsi.getSrc(0).getSwizzle(c)]);
> +*/
> }
>
> // For formatted stores, the write mask on OP_SUSTP can be used.
> @@ -2374,8 +2383,9 @@ Converter::handleSTORE()
> int c;
> std::vector<Value *> off, src, dummy;
>
> - if (tgsi.getDst(0).get...
2014 May 18
1
[PATCH 1/2] nv50/ir: fix s32 x s32 -> high s32 multiply logic
...etSSA(1, FILE_FLAGS);
- for (int j = 0; j < 4; ++j)
+ for (int j = 0; j < 5; ++j)
r[j] = bld->getSSA(fullSize);
i[8] = bld->mkOp2(OP_SHR, fTy, r[0], t[1], bld->mkImm(halfSize * 8));
i[6] = bld->mkOp2(OP_ADD, fTy, r[1], r[0], imm);
bld->mkMov(r[3], r[0])->setPredicate(CC_NC, c[0]);
bld->mkOp2(OP_UNION, TYPE_U32, r[2], r[1], r[3]);
- i[5] = bld->mkOp3(OP_MAD, fTy, mul->getDef(0), a[1], b[1], r[2]);
+ i[5] = bld->mkOp3(OP_MAD, fTy, r[4], a[1], b[1], r[2]);
// set carry defs / sources
i[3]-&g...
2016 Sep 28
0
[PATCH] nv50/ir: constant fold OP_SPLIT
...U16 : TYPE_S16;
> + }
> + if (i->sType == TYPE_U16 || i->sType == TYPE_S16) {
> + shift = 8;
> + type = (i->sType == TYPE_U16) ? TYPE_U8 : TYPE_S8;
> + }
shift = typeSizeOf(i->dType);
> + if (type != TYPE_NONE) {
> + bld.mkMov(i->getDef(0), bld.mkImm(imm0.reg.data.u64 >> shift), type);
> + bld.mkMov(i->getDef(1), bld.mkImm(imm0.reg.data.u64), type);
u64 val = ...u64;
for (d = 0; i->defExists(d); ++d) {
bld.mkMov(i->getDef(d), bld.mkImm(val & ((1 << shift) - 1));
val >>= s...
2016 Mar 17
4
[PATCH mesa v2 1/3] nouveau: codegen: Disable more old resource handling code
...return;
}
+/* Keep this around for now as reference when adding img support
getResourceCoords(off, r, 1);
if (isResourceRaw(code, r)) {
@@ -2355,6 +2360,7 @@ Converter::handleLOAD(Value *dst0[4])
FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
if (dst0[c] != def[c])
mkMov(dst0[c], def[tgsi.getSrc(0).getSwizzle(c)]);
+*/
}
// For formatted stores, the write mask on OP_SUSTP can be used.
@@ -2391,6 +2397,7 @@ Converter::handleSTORE()
return;
}
+/* Keep this around for now as reference when adding img support
getResourceCoords(off, r, 0);
src =...
2016 Sep 30
2
[PATCH v2] nv50/ir: constant fold OP_SPLIT
...Type),
+ isSignedType(i->dType));
+ if (likely(type != TYPE_NONE)) {
+ uint64_t val = imm0.reg.data.u64;
+ uint16_t shift = size * 8;
+ bld.setPosition(i, false);
+ for (int8_t d = 0; i->defExists(d); ++d) {
+ bld.mkMov(i->getDef(d), bld.mkImm(val & ((1 << shift) - 1)), type);
+ val >>= shift;
+ }
+ delete_Instruction(prog, i);
+ }
+ }
+ break;
case OP_MUL:
if (i->dType == TYPE_F32)
tryCollapseChainedMULs(i, s, imm0);
--
2.10.0
2016 Mar 16
0
[PATCH mesa 6/6] nouveau: codegen: Disable more old resource handling code
...AD");
}
+/* Keep this around for now as reference when adding img support
getResourceCoords(off, r, 1);
if (isResourceRaw(code, r)) {
@@ -2363,6 +2371,7 @@ Converter::handleLOAD(Value *dst0[4])
FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
if (dst0[c] != def[c])
mkMov(dst0[c], def[tgsi.getSrc(0).getSwizzle(c)]);
+*/
}
// For formatted stores, the write mask on OP_SUSTP can be used.
@@ -2374,8 +2383,9 @@ Converter::handleSTORE()
int c;
std::vector<Value *> off, src, dummy;
- if (tgsi.getDst(0).getFile() == TGSI_FILE_BUFFER ||
- tgsi.ge...
2016 Mar 16
0
[PATCH mesa 6/6] nouveau: codegen: Disable more old resource handling code
...adding img support
>> getResourceCoords(off, r, 1);
>>
>> if (isResourceRaw(code, r)) {
>> @@ -2363,6 +2371,7 @@ Converter::handleLOAD(Value *dst0[4])
>> FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
>> if (dst0[c] != def[c])
>> mkMov(dst0[c], def[tgsi.getSrc(0).getSwizzle(c)]);
>> +*/
>> }
>>
>> // For formatted stores, the write mask on OP_SUSTP can be used.
>> @@ -2374,8 +2383,9 @@ Converter::handleSTORE()
>> int c;
>> std::vector<Value *> off, src, dummy;
>>...
2016 Oct 02
2
[PATCH] nv50/ir: Propagate third immediate src when folding OP_MAD
...mod;
i->setSrc(1, NULL);
i->setSrc(2, NULL);
- i->op = i->src(0).mod.getOp();
- if (i->op != OP_CVT)
- i->src(0).mod = 0;
+ if (i->src(0).getImmediate(imm1)) {
+ bld.setPosition(i, false);
+ newi = bld.mkMov(i->getDef(0), bld.mkImm(imm1.reg.data.u64),
+ i->dType);
+ delete_Instruction(prog, i);
+ }
+ else {
+ i->op = i->src(0).mod.getOp();
+ if (i->op != OP_CVT)
+ i->src(0).mod = 0;
+ }...
2019 Oct 14
1
[PATCH] gm107/ir: fix loading z offset for layered 3d image bindings
...8),
- loadSuInfo32(ind, slot, NVC0_SU_INFO_BSIZE, su->tex.bindless),
- pred->getDef(0));
+ ValueDef &def = su->def(i);
+ ValueDef &def2 = su2d->def(i);
+ Instruction *mov = NULL;
+
+ if (pred) {
+ mov = bld.mkMov(bld.getSSA(), bld.loadImm(NULL, 0));
+ mov->setPredicate(CC_P, pred->getDef(0));
+ }
+
+ Instruction *uni = ret[i] = bld.mkOp2(OP_UNION, TYPE_U32,
+ bld.getSSA(),
+ NULL, def2.get());
+...
2015 Feb 23
2
[PATCH 1/2] nv50/ir: add fp64 support on G200 (NVA0)
...SSA(1, FILE_FLAGS);
+ bld.mkOp2(OP_AND, TYPE_U32, NULL, input[1], bld.loadImm(NULL, 1))
+ ->setFlagsDef(0, pred);
+ shr[2] = bld.getSSA(4); shr[3] = bld.getSSA(4);
+ bld.mkOp2(OP_OR, TYPE_U32, shr[2], shr[0], bld.loadImm(NULL, 0x80000000))
+ ->setPredicate(CC_S, pred);
+ bld.mkMov(shr[3], shr[0])
+ ->setPredicate(CC_NS, pred);
+ shr[0] = bld.mkOp2v(OP_UNION, TYPE_U32, bld.getSSA(4), shr[2], shr[3]);
+
+ guess = bld.mkOp2v(OP_SUB, TYPE_F64, bld.getSSA(8), guess,
+ bld.mkOp2v(OP_MERGE, TYPE_F64, bld.getSSA(8), shr[0], shr[1]));
+
+ if (i->...
2016 Mar 14
2
[RFC mesa] nouveau: Add support for OpenCL global memory buffers
...e if (i->src(0).getFile() == FILE_MEMORY_GLOBAL) {
Value *ind = i->getIndirect(0, 1);
Value *ptr = loadResInfo64(ind, i->getSrc(0)->reg.fileIndex * 16);
@@ -2126,6 +2127,7 @@ NVC0LoweringPass::visit(Instruction *i)
if (i->defExists(0)) {
bld.mkMov(i->getDef(0), bld.mkImm(0));
}
+#endif
}
break;
case OP_ATOM:
--
2.7.2
2016 Oct 02
2
[PATCH] nv50/ir: Propagate third immediate src when folding OP_MAD
...setSrc(2, NULL);
>> - i->op = i->src(0).mod.getOp();
>> - if (i->op != OP_CVT)
>> - i->src(0).mod = 0;
>> + if (i->src(0).getImmediate(imm1)) {
>> + bld.setPosition(i, false);
>> + newi = bld.mkMov(i->getDef(0), bld.mkImm(imm1.reg.data.u64),
>> + i->dType);
>> + delete_Instruction(prog, i);
> What's an example of a situation where this helps? It shouldn't
> matter, the mov's should get cleaned up. [Clearly 17 shaders
&...
2016 Mar 14
2
[RFC mesa] nouveau: Add support for OpenCL global memory buffers
...> Value *ind = i->getIndirect(0, 1);
>> Value *ptr = loadResInfo64(ind, i->getSrc(0)->reg.fileIndex *
>> 16);
>> @@ -2126,6 +2127,7 @@ NVC0LoweringPass::visit(Instruction *i)
>> if (i->defExists(0)) {
>> bld.mkMov(i->getDef(0), bld.mkImm(0));
>> }
>> +#endif
>> }
>> break;
>> case OP_ATOM:
>> --
>> 2.7.2
>>
>>
>
2015 Feb 23
2
[Mesa-dev] [PATCH 2/2] nvc0/ir: improve precision of double RCP/RSQ results
...4, bld.getSSA(8), guess,
> + bld.mkOp3v(OP_MAD, TYPE_F64, bld.getSSA(8), half_input,
> + bld.mkOp2v(OP_MUL, TYPE_F64, bld.getSSA(8), guess, guess),
> + three_half));
> + }
> +
> + bld.mkMov(def, guess);
> }
>
> bool
>