search for: misneedchainedge

Hello, While tuning the MIScheduler for my target, I discovered a code that unnecessarily restricts the scheduler. I think this is a bug, but I would appreciate a second opinion. In file ScheduleDAGInstrs.cpp, the function MIsNeedChainEdge determines whether two MachineInstrs are ordered by a memory dependence. It first runs through the standard criteria (Do both instructions access memory? Does at least one store to memory? Is either access volatile? etc.), and finally queries AliasAnalysis if available. Before reaching alias a...

Hi, I write again regarding buildSchedGraph(), as I am still not happy about things there. I have found at least two examples which do not work out: 1) SU(2) Store "Value A" SU(1) Store "Value A" SU(0) Load "Value A" If MIsNeedChainEdge() returns false for SU(0) and SU(1), SU(0) is inserted into RejectedMemNodes and removed from its MemUses SU list, as this list is cleared. Therefore SU(2) must be handled with adjustChainDeps(), because it needs an edge from SU(0). For some reason adjustChainDeps() was only called for may-aliasing...

...bject: RE: ScheduleDAGInstrs.cpp > > Hi Jonas, > > How is your target implementing areMemAccessesTriviallyDisjoint? The > callback is there so that we don't get into the situation where the > call to isIdentifiedObject (which is called from isUnsafeMemoryObject > from MIsNeedChainEdge) results in the edge being added between two > memory locations that the target can easily prove are different (e.g > based on base register + index + offset, etc). > > Are you seeing the problem during pre-RA scheduling or post-RA > scheduling? > > I think we may be able...

...dencies from a load are expected to be >higher latency, so they are good candidates to stop the search. I cannot say I understand your answer, unfortunately, and to clarify all this eventually, I will explain my point of view: I think there are cases where adjustSchedDeps() MUST make a call to MIsNeedChainEdge() between to specific SUs, or the DAG will remain illegal. Here is my little example again, where SU(0) and SU(2) have a store - load memory dependence which must be modelled with an edge. SUnits: SU(0) Store to address A SU(1) Store to address B SU(2) Load from address A DAG building, bottom-up:...

...ade a fix for it quickly just to illustrate what the problem is (one of the previously attached patches). Basically, when an SU's underlying objects are analyzed, the results are remembered by putting the SU into one or both of the (added) sets AliasMemUseDefMIs and NonAliasMemUseDefMIs. Later, MIsNeedChainEdge() can return false, if they were originally in different domains: // A NonAliasing node cannot alias an AliasingNode. This is the case // where MIa had only non-aliasing underlying objects and MIb had // only aliasing underlying objects, or vice versa. if ((AliasMemUseDefMIs.count(MIa) &am...

Hi, (This only concerns MISNeedChainEdge(), and is separate from D8705) I found out that the MIScheduler (pre-ra) could not handle a simple test case (test/CodeGen/SystemZ/alias-01.ll), with 16 independent load / add / stores. The buildSchedGraph() put too many edges between memory accesses, because 1) There was no implementation of a...

...> > > > 1. A new alias chain add deps to all possibly aliasing SUs, and then > clears those lists. > > 2. When AliasChain is present, the addChainDependency() method is > called, > > but the target hook areMemAccessesTriviallyDisjoint() called inside > > MIsNeedChainEdge() allows this edge to be skipped. > > > > This means that I get a case where > > > > SU0 > > > > SU1, AliasChain > > /\ > > / \ // Aliasing memory accesses > > SU2 > > > > all SUs have memory operands, but the underlyi...

...od? I find the handling of AliasChain is disturbing since: 1. A new alias chain add deps to all possibly aliasing SUs, and then clears those lists. 2. When AliasChain is present, the addChainDependency() method is called, but the target hook areMemAccessesTriviallyDisjoint() called inside MIsNeedChainEdge() allows this edge to be skipped. This means that I get a case where SU0 SU1, AliasChain /\ / \ // Aliasing memory accesses SU2 all SUs have memory operands, but the underlying objects vectors...

...would handle this... And BasicAliasAnalysis >> does >> >> if (V1 == V2) return MustAlias; >> >> , so I'm not sure how this would be done .. ? > > If you run with -enable-misched -enable-aa-sched-mi > > then you'll get this logic from the end of MIsNeedChainEdge: > > // The following interface to AA is fashioned after DAGCombiner::isAlias > // and operates with MachineMemOperand offset with some important > // assumptions: > // - LLVM fundamentally assumes flat address spaces. > // - MachineOperand offset can *only* result from...

...;t see how > AliasAnalysis::Location would handle this... And BasicAliasAnalysis > does > > if (V1 == V2) return MustAlias; > > , so I'm not sure how this would be done .. ? If you run with -enable-misched -enable-aa-sched-mi then you'll get this logic from the end of MIsNeedChainEdge: // The following interface to AA is fashioned after DAGCombiner::isAlias // and operates with MachineMemOperand offset with some important // assumptions: // - LLVM fundamentally assumes flat address spaces. // - MachineOperand offset can *only* result from legalization and //...

Hi Hal, Thanks. How about a symbol with two different immediate offsets - the Value* would be the same, right? I don't see how AliasAnalysis::Location would handle this... And BasicAliasAnalysis does if (V1 == V2) return MustAlias; , so I'm not sure how this would be done .. ? /Jonas > -----Original Message----- > From: Hal Finkel [mailto:hfinkel at anl.gov] > Sent:

...> >> does > >> > >> if (V1 == V2) return MustAlias; > >> > >> , so I'm not sure how this would be done .. ? > > > > If you run with -enable-misched -enable-aa-sched-mi > > > > then you'll get this logic from the end of MIsNeedChainEdge: > > > > // The following interface to AA is fashioned after > > DAGCombiner::isAlias > > // and operates with MachineMemOperand offset with some important > > // assumptions: > > // - LLVM fundamentally assumes flat address spaces. > > // - Mach...

...So the question much more likely is: Why AA sees these two objects as not aliasing, and are they properly described and presented to it? Does ld/bitcast has proper memory operands? Any flags on them? Is underlying memory object making sense? You can look at getUnderlyingObjectForInstr and MIsNeedChainEdge in the MI scheduling framework to see what I mean. If you are still using SDNode scheduling framework - it has a very similar functionality in a slightly different code. Hope this helps. Sergei --- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Founda...

...wo objects as not > > aliasing, and are they properly described and presented to it? > > > > Does ld/bitcast has proper memory operands? Any flags on them? Is > > underlying memory object making sense? > > > > You can look at getUnderlyingObjectForInstr and MIsNeedChainEdge in the MI > > scheduling framework to see what I mean. > > > > If you are still using SDNode scheduling framework - it has a very similar > > functionality in a slightly different code. > > > > Hope this helps. > > > > Sergei > > > &g...

...likely is: Why AA sees these two objects as not > aliasing, and are they properly described and presented to it? > > Does ld/bitcast has proper memory operands? Any flags on them? Is > underlying memory object making sense? > > You can look at getUnderlyingObjectForInstr and MIsNeedChainEdge in the MI > scheduling framework to see what I mean. > > If you are still using SDNode scheduling framework - it has a very similar > functionality in a slightly different code. > > Hope this helps. > > Sergei > > --- > Qualcomm Innovation Center, Inc. is a...

...t; aliasing, and are they properly described and presented to it? > > > > > > Does ld/bitcast has proper memory operands? Any flags on them? Is > > > underlying memory object making sense? > > > > > > You can look at getUnderlyingObjectForInstr and MIsNeedChainEdge in the MI > > > scheduling framework to see what I mean. > > > > > > If you are still using SDNode scheduling framework - it has a very similar > > > functionality in a slightly different code. > > > > > > Hope this helps. > > >...

Here's another data point that may be useful. [Scheduling experts, please help! :) ] If the two-byte bitfield is replaced by a two-byte struct (replace "short i:8" with "short i", etc.), the scheduler properly generates a dependency between the store and the load. For this case, a GEP is used instead of a bitcast:

Greetings, I'm investigating a bug in the PowerPC back end in which a load from a storage address is being reordered prior to a store to the same storage address. I'm quite new to LLVM, so I would appreciate some help understanding what I'm seeing from the dumps. I assume that some information is missing that would represent the memory dependency, but I don't know what form that