search for: mischeduler

Hi, Regarding the mischeduler, I wonder // For loops that are acyclic path limited, aggressively schedule for // latency. This can result in very long dependence chains scheduled in // sequence, so once every cycle (when CurrMOps == 0), switch to normal // heuristics. if (Rem.IsAcyclicLatencyLimited && !Zone->getCu...

Hi, I am looking at the Hexagon MI Scheduling and trying to adapt it to my target. As far as I can see, Hexagon does not bundle the VLIW-bundles by calling bundleWithPred() on MIs of the completed cycle. First of all, why is this not done? SlotIndexes seems to have at least some support for this, by calling getBundleStart() for each MI that is looked up. A follow up question is then, how would

...n't see that they are defined in the block when walking through the operands for these instructions. The peak pressure printouts from ScheduleDAGMILive look like they are accounting for AH and AL being live because the corresponding pressure sets for these register classes are increased. In the mischeduler is there a way to discover that these two registers may be contributing to peak pressure in the block? Thanks, Austin Kerbow -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20170812/9cf0103b/attachment...

...B %vreg2<def> = COPY %vreg11 , %vreg11 and %vreg2 could have been coalesced (%vreg11 is unused outside this block) My question is how to best handle this. * Seems to me probably best to handle this pre-ra if possible, even though cases like this may be handled later. * Pre-RA mischeduler is run after the coalescer, so that's not going to work. thanks for any help, Jonas

> > Of course, you want to duplicate as little of the generic scheduling logic > as you can. So I think the challenge is how to expose the > generic scheduler's functionality as a base class or composition of > utilities so that defining your strategy doesn't require too much > copy-paste. ​Isn't GCNMaxOccupancySchedStrategy [1] already an example on using

Hello, While tuning the MIScheduler for my target, I discovered a code that unnecessarily restricts the scheduler. I think this is a bug, but I would appreciate a second opinion. In file ScheduleDAGInstrs.cpp, the function MIsNeedChainEdge determines whether two MachineInstrs are ordered by a memory dependence. It first runs thro...

Hi, I have been experimenting for a while with tryCandidate() method of the pre-RA mischeduler. I have by chance found some parameters that give quite good results on benchmarks on SystemZ (on average 1% improvement, some improvements of several percent and very little regressions). Basically, I add a "latency heuristic boost" just above processor resources checking: tryCandid...

...new target which is a fairly > simple in-order execution machine. > > I've been watching this presentation from a 2014 LLVM dev meeting as it > seems relevant: > > "SchedMachineModel: Adding and Optimizing a Subtarget" > http://llvm.org/devmtg/2014-10/Slides/Estes-MISchedulerTutorial.pdf > > In this presentation the author says that there have been several ways to > approach scheduling in LLVM over the years: > > - Pre 2008: SelectionDAGISel pass creates the ScheduleDAG from the > SelectionDAG at the end of instruction selection > - Schedul...

...add instruction scheduling for a new target which is a fairly simple in-order execution machine. I've been watching this presentation from a 2014 LLVM dev meeting as it seems relevant: "SchedMachineModel: Adding and Optimizing a Subtarget" http://llvm.org/devmtg/2014-10/Slides/Estes-MISchedulerTutorial.pdf In this presentation the author says that there have been several ways to approach scheduling in LLVM over the years: * Pre 2008: SelectionDAGISel pass creates the ScheduleDAG from the SelectionDAG at the end of instruction selection * ScheduleDAG works on SelectionDAG Nodes (S...

...ing on instruction bundles. Ideally, I'd like to have bundles *before* RA to model certain constraints, e.g. the exposed one by Tzu-Chien a while ago in his thread http://lists.cs.uiuc.edu/pipermail/llvmdev/2005-September/004798.html In order to build bundles, we have added a new bottom-up MIScheduler, right after reg coalescing, which behaves much like ScheduleDAGVLIW but without hazard recognizing. Due to some tricky instructions, we cannot schedule on the DAG. Bundles are built at exitRegion() in the scheduling process and the live interval information is updated correctly. After this, t...

...http://lists.cs.uiuc.edu/pipermail/llvmdev/2005-September/004798.html The bundle support in the tree should handle constraints like that. The register allocator basically sees bundles as single instructions when computing interference. > In order to build bundles, we have added a new bottom-up MIScheduler, > right after reg coalescing, which behaves much like ScheduleDAGVLIW but > without hazard recognizing. Due to some tricky instructions, we cannot > schedule on the DAG. Bundles are built at exitRegion() in the scheduling > process and the live interval information is updated corre...

> On Aug 30, 2017, at 1:43 PM, Matthias Braun <matze at braunis.de> wrote: > > That means you cannot use the code from RegisterPressure.{cpp|h} to compute this. The other liveness analysis we have in llvm codegen is LiveIntervals (LiveItnervalAnalysis) which gives you a list of liveness segments of a given vreg (the same representation is used in most linear scan allocators even

Hi, (This only concerns MISNeedChainEdge(), and is separate from D8705) I found out that the MIScheduler (pre-ra) could not handle a simple test case (test/CodeGen/SystemZ/alias-01.ll), with 16 independent load / add / stores. The buildSchedGraph() put too many edges between memory accesses, because 1) There was no implementation of areMemAccessesTriviallyDisjoint() for SystemZ. 2) Type Based Alia...

...iuc.edu/pipermail/llvmdev/2005-September/004798.html The bundle support in the tree should handle constraints like that. The register allocator basically sees bundles as single instructions when computing interference. > In order to build bundles, we have added a new bottom-up MIScheduler, > right after reg coalescing, which behaves much like ScheduleDAGVLIW but > without hazard recognizing. Due to some tricky instructions, we cannot > schedule on the DAG. Bundles are built at exitRegion() in the scheduling > process and the live interval...

...Phil, > I've been watching this presentation from a 2014 LLVM dev meeting Thanks for your sharing! I am reviewing: * The chapter 10 (Instruction Level Parallelism) and chapter 11 (Optimizing for Parallelism and Locality) of Compiler Principle[1] * Adding and Optimizing a Subtarget for MIScheduler[2] by Dave Estes * Scheduler for in-order processors - what's present and what's missing in LLVM[3] by Javed Absar * Writing Great Machine Schedulers[4] by Javed Absar and Florian Hahn Hi Alex, Please leading me to implement Machine scheduling model for at least one core (e.g. Rocket...

...ttp://lists.cs.uiuc.edu/pipermail/llvmdev/2005-September/004798.html The bundle support in the tree should handle constraints like that. The register allocator basically sees bundles as single instructions when computing interference. > In order to build bundles, we have added a new bottom-up MIScheduler, > right after reg coalescing, which behaves much like ScheduleDAGVLIW but > without hazard recognizing. Due to some tricky instructions, we cannot > schedule on the DAG. Bundles are built at exitRegion() in the scheduling > process and the live interval information is updated correctly...

...determining live-through information requires a separate global liveness analysis, because LiveIntervals doesn’t tell you “what’s live at this point”. -Andy Ghassan, have you managed to try this, yet? This seems interesting to me on SystemZ, as I am still seeing increased spilling when activating mischeduler for SystemZ and switching to isel source-order scheduling. /Jonas -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20170912/c9528496/attachment.html>