search for: mipspat

...re some simple patterns from the MipsInstrInfo.td //===----------------------------------------------------------------------===// // Arbitrary patterns that map to one or more instructions //===----------------------------------------------------------------------===// // Small immediates def : MipsPat<(i32 immSExt16:$in), (ADDiu ZERO, imm:$in)>; def : MipsPat<(i32 immZExt16:$in), (ORi ZERO, imm:$in)>; def : MipsPat<(i32 immLow16Zero:$in), (LUi (HI16 imm:$in))>; Here are some which have several instructions multiclass SetgePats<R...

Thanks for your reply. We are trying to implement a simple Mips-based CPU with just for teaching purpose, so we delete some instructions which are not commonly used, thus the task won't be too hard for students. I am responsible for modifying the compiler so that the compiler won't emit unsupported instructions. In order to avoid "can not select" error, I am trying to expand

...ons+data has changed slightly. I've investigated further and I'm fairly confident that r235869 (http://llvm.org/viewvc/llvm-project?view=revision&revision=235869) is the cause of this regression. The problem is these three definitions: // Bypass trunc nodes for bitwise ops. def : MipsPat<(i32 (trunc (and GPR64:$lhs, GPR64:$rhs))), (EXTRACT_SUBREG (AND64 GPR64:$lhs, GPR64:$rhs), sub_32)>; def : MipsPat<(i32 (trunc (or GPR64:$lhs, GPR64:$rhs))), (EXTRACT_SUBREG (OR64 GPR64:$lhs, GPR64:$rhs), sub_32)>; def : MipsPat<(i32 (trunc (xor G...

Hi, I have tagged the 3.6.1-rc1 so testing can begin. We can always use more testers, so if you are interested in helping, let me know. Instructions for validating an LLVM release can be found here: http://llvm.org/docs/ReleaseProcess.html Reminder: We are using 3.6.0 as our baseline for regression testing. Thanks, Tom

...teness sake I've included this, but it's return true there are bits in both 16 bit fragments. Then we use (here VT = i32, ORiOp is our logical or which takes an immediate, LUiOp loads the upper bits of a register with an immediate, zeroing the lower 16 bits): // Arbitrary immediates def : MipsPat<(VT LUiORiPred:$imm), (ORiOp (LUiOp (HI16 imm:$imm)), (LO16 imm:$imm))>; This anonymous pattern matches any sign-extended 32 bit immediate due to LUiORiPred, and the expression (HI16 imm:$imm) takes an immediate and extracts the upper bits of the immediate into a constant which LUiOp accepts...

Hi all, This seems like a dumb question but while setting up a pattern in TD file, I got stuck on trying to get each half of an immediate as the half-sized type (ie. i64 imm -> pair of i32 imm's). Is there an existing way to do it? I've tried the 'EXTRACT_SUBREG' but that seems to error at the end of scheduling. Looking at Target.td, I'm not sure which opcode is meant