Displaying 13 results from an estimated 13 matches for "mipsinstrformats".
2011 May 07
3
[LLVMdev] [MIPS] some type errors in the commentary of *.td file.
On Sat, May 7, 2011 at 12:33 PM, Eric Christopher <echristo at apple.com> wrote:
>
> On May 5, 2011, at 11:26 PM, Liu wrote:
>
>> some some type errors in the commentary of *.td file.
>> such as:
>> lib/Target/Mips/MipsInstrFormats.td
>> MipsRegisterInfo.td - Mips Register defs
>> it should be
>> MipsInstrFormats.td - Mips Instruction Formats
>>
>> lib/Target/Mips/MipsInstrInfo.td
>> MipsInstrInfo.td - Mips Register defs
>> it should be
>> MipsInstrInfo.td - Target Description f...
2011 May 09
0
[LLVMdev] [MIPS] some type errors in the commentary of *.td file.
...:47 AM, Liu wrote:
> On Sat, May 7, 2011 at 12:33 PM, Eric Christopher <echristo at apple.com> wrote:
>>
>> On May 5, 2011, at 11:26 PM, Liu wrote:
>>
>>> some some type errors in the commentary of *.td file.
>>> such as:
>>> lib/Target/Mips/MipsInstrFormats.td
>>> MipsRegisterInfo.td - Mips Register defs
>>> it should be
>>> MipsInstrFormats.td - Mips Instruction Formats
>>>
>>> lib/Target/Mips/MipsInstrInfo.td
>>> MipsInstrInfo.td - Mips Register defs
>>> it should be
>>> MipsIn...
2011 May 06
2
[LLVMdev] [MIPS] some type errors in the commentary of *.td file.
Hi all,
I find some some type errors in the commentary of *.td file.
such as:
lib/Target/Mips/MipsInstrFormats.td
MipsRegisterInfo.td - Mips Register defs
it should be
MipsInstrFormats.td - Mips Instruction Formats
lib/Target/Mips/MipsInstrInfo.td
MipsInstrInfo.td - Mips Register defs
it should be
MipsInstrInfo.td - Target Description for Mips Target
and some thing I think it is wrong in lib/Target/Mips/M...
2011 May 07
0
[LLVMdev] [MIPS] some type errors in the commentary of *.td file.
On May 5, 2011, at 11:26 PM, Liu wrote:
> some some type errors in the commentary of *.td file.
> such as:
> lib/Target/Mips/MipsInstrFormats.td
> MipsRegisterInfo.td - Mips Register defs
> it should be
> MipsInstrFormats.td - Mips Instruction Formats
>
> lib/Target/Mips/MipsInstrInfo.td
> MipsInstrInfo.td - Mips Register defs
> it should be
> MipsInstrInfo.td - Target Description for Mips Target
>
> and s...
2011 Oct 07
2
[LLVMdev] MIPS 32bit code generation
Hi,
I noticed one class in MipsInstrFormats.td:L46 -> Class MipsPseudo. I
wonder whether I can use this. If does, I wonder what would be the right way
to use. Thanks,
On Thu, Oct 6, 2011 at 11:29 AM, Akira Hatanaka <ahatanak at gmail.com> wrote:
> Do you want to replace
>
> lui $2, %hi(g1)
> addiu $2, $2, %lo(g1)
&g...
2011 Oct 07
0
[LLVMdev] MIPS 32bit code generation
I reiterate. You should fix the simulator. It is broken. The compiler is not. Fix what's broken.
-Jim
On Oct 7, 2011, at 1:11 PM, Gang-Ryung Uh wrote:
> Hi,
>
> I noticed one class in MipsInstrFormats.td:L46 -> Class MipsPseudo. I wonder whether I can use this. If does, I wonder what would be the right way to use. Thanks,
>
>
>
> On Thu, Oct 6, 2011 at 11:29 AM, Akira Hatanaka <ahatanak at gmail.com> wrote:
> Do you want to replace
>
> lui $2, %hi(g1)
> addi...
2011 Oct 07
1
[LLVMdev] MIPS 32bit code generation
...Grosbach <grosbach at apple.com> wrote:
> I reiterate. You should fix the simulator. It is broken. The compiler is
> not. Fix what's broken.
>
> -Jim
>
> On Oct 7, 2011, at 1:11 PM, Gang-Ryung Uh wrote:
>
> > Hi,
> >
> > I noticed one class in MipsInstrFormats.td:L46 -> Class MipsPseudo.
> I wonder whether I can use this. If does, I wonder what would be the right
> way to use. Thanks,
> >
> >
> >
> > On Thu, Oct 6, 2011 at 11:29 AM, Akira Hatanaka <ahatanak at gmail.com>
> wrote:
> > Do you want to replace...
2016 Nov 23
4
RFC: code size reduction in X86 by replacing EVEX with VEX encoding
Hi All.
This is an RFC for a proposed target specific X86 optimization for reducing code size in the encoding of AVX-512 instructions when possible.
When the AVX512F instruction set was introduced in X86 it included additional 32 registers of 512bit size each ZMM0 - ZMM31, as well as additional 16 XMM registers XMM16-XMM31 and 16 YMM registers YMM16-YMM31.
In order to encode the new registers of
2016 Nov 23
2
RFC: code size reduction in X86 by replacing EVEX with VEX encoding
...for you
> instead of manually making a table yourself. TableGen has a feature that is
> specifically designed to make mapping tables like this. For examples, grep
> for InstrMapping in:
>
> lib/Target/Hexagon/Hexagon.td
> lib/Target/Mips/MipsDSPInstrFormats.td
> lib/Target/Mips/MipsInstrFormats.td
> lib/Target/Mips/Mips32r6InstrFormats.td
> lib/Target/PowerPC/PPC.td
> lib/Target/AMDGPU/SIInstrInfo.td
> lib/Target/AMDGPU/R600Instructions.td
> lib/Target/SystemZ/SystemZInstrFormats.td
> lib/Target/Lanai/LanaiInstrInfo.td
>
> I've used this feature a few times in...
2011 Oct 06
0
[LLVMdev] MIPS 32bit code generation
Do you want to replace
lui $2, %hi(g1)
addiu $2, $2, %lo(g1)
with this?
la $2, g1
If that is the case, you can add this pattern.
def op_la : Operand<i32>;
def LA :
FI<0x09, (outs CPURegs:$dst), (ins op_la:$addr0, op_la:$addr1),
"la $dst, $addr0", [(set CPURegs:$dst,
(add (MipsHi tglobaladdr:$addr0), (MipsLo
tglobaladdr:$addr1)))], IIAlu>;
2016 Nov 24
3
RFC: code size reduction in X86 by replacing EVEX with VEX encoding
...bleGen generate the mapping table for you instead of manually making a table yourself. TableGen has a feature that is specifically designed to make mapping tables like this. For examples, grep for InstrMapping in:
lib/Target/Hexagon/Hexagon.td
lib/Target/Mips/MipsDSPInstrFormats.td
lib/Target/Mips/MipsInstrFormats.td
lib/Target/Mips/Mips32r6InstrFormats.td
lib/Target/PowerPC/PPC.td
lib/Target/AMDGPU/SIInstrInfo.td
lib/Target/AMDGPU/R600Instructions.td
lib/Target/SystemZ/SystemZInstrFormats.td
lib/Target/Lanai/LanaiInstrInfo.td
I've used this feature a few times in the PowerPC backend, and it's quite...
2016 Nov 28
2
RFC: code size reduction in X86 by replacing EVEX with VEX encoding
...bleGen generate the mapping table for you instead of manually making a table yourself. TableGen has a feature that is specifically designed to make mapping tables like this. For examples, grep for InstrMapping in:
lib/Target/Hexagon/Hexagon.td
lib/Target/Mips/MipsDSPInstrFormats.td
lib/Target/Mips/MipsInstrFormats.td
lib/Target/Mips/Mips32r6InstrFormats.td
lib/Target/PowerPC/PPC.td
lib/Target/AMDGPU/SIInstrInfo.td
lib/Target/AMDGPU/R600Instructions.td
lib/Target/SystemZ/SystemZInstrFormats.td
lib/Target/Lanai/LanaiInstrInfo.td
I've used this feature a few times in the PowerPC backend, and it's quite...
2011 Oct 05
4
[LLVMdev] MIPS 32bit code generation
Hi,
In order to emit "la $4,ADDR" instead of lui followed by addiu to load
the data address, could you advise what is proper way to revise td files in
the MIPS target?
Thanks,
--
Gang-Ryung Uh, Associate Professor
Department of Computer Science
College of Engineering, Boise State Univerisity
tel: 1 208 426-5691 e-mail:guh at boisestate.edu
http://cs.boisestate.edu/~uh