Displaying 5 results from an estimated 5 matches for "mipsgprreg".
2012 Jan 31
4
[LLVMdev] (MC) Register parsing for AsmParser (standalone assembler)
...ets:
*********************************
The Mips architecture has register names that are context sensitive.
For instance, the 32 general purpose registers for both Mips32 and Mips64 have the same name, but each of the Mips32 registers are just a subregister in their Mips64 instance.
def AT : MipsGPRReg< 1, "AT">, DwarfRegNum<[1]>;
def AT_64 : Mips64GPRReg< 1, "AT", [AT]>;
It gets more interesting with floating point where we have 3 different configurations, single precision, double precision aliased with single precision pair and straight double poin...
2012 Mar 21
4
[LLVMdev] apparent mistake in several ports register td file ???
...register file for 64-bit floating-point values.
class Rd<bits<5> num, string n, list<Register> subregs> : SparcReg<n> {
let Num = num;
let SubRegs = subregs;
let SubRegIndices = [sub_even, sub_odd];
let CoveredBySubRegs = 1;
}
......
// Mips CPU Registers
class MipsGPRReg<bits<5> num, string n> : MipsReg<n> {
let Num = num;
}
2012 Mar 23
0
[LLVMdev] apparent mistake in several ports register td file ???
...ss Rd<bits<5> num, string n, list<Register> subregs> : SparcReg<n> {
> let Num = num;
> let SubRegs = subregs;
> let SubRegIndices = [sub_even, sub_odd];
> let CoveredBySubRegs = 1;
> }
>
> ......
> // Mips CPU Registers
> class MipsGPRReg<bits<5> num, string n> : MipsReg<n> {
> let Num = num;
> }
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2012 Feb 02
0
[LLVMdev] (MC) Register parsing for AsmParser (standalone assembler)
...*******
>
> The Mips architecture has register names that are context sensitive.
>
> For instance, the 32 general purpose registers for both Mips32 and Mips64 have the same name, but each of the Mips32 registers are just a subregister in their Mips64 instance.
>
> def AT : MipsGPRReg< 1, "AT">, DwarfRegNum<[1]>;
> def AT_64 : Mips64GPRReg< 1, "AT", [AT]>;
>
> It gets more interesting with floating point where we have 3 different configurations, single precision, double precision aliased with single precision pair and strai...
2012 Feb 03
0
[LLVMdev] (MC) Register parsing for AsmParser (standalone assembler)
...*******
>
> The Mips architecture has register names that are context sensitive.
>
> For instance, the 32 general purpose registers for both Mips32 and Mips64 have the same name, but each of the Mips32 registers are just a subregister in their Mips64 instance.
>
> def AT : MipsGPRReg< 1, "AT">, DwarfRegNum<[1]>;
> def AT_64 : Mips64GPRReg< 1, "AT", [AT]>;
>
> It gets more interesting with floating point where we have 3 different configurations, single precision, double precision aliased with single precision pair and strai...