Displaying 2 results from an estimated 2 matches for "mipsgenmcpseudolowering".
2014 Apr 24
3
[LLVMdev] tablegen for fast isel
...itter.inc \
MipsGenDAGISel.inc MipsGenCallingConv.inc \
- MipsGenSubtargetInfo.inc MipsGenMCCodeEmitter.inc \
+ MipsGenSubtargetInfo.inc MipsGenFastISel.inc
MipsGenMCCodeEmitter.inc \
MipsGenDisassemblerTables.inc \
MipsGenMCPseudoLowering.inc MipsGenAsmMatcher.inc
I get an error.
Included from
/home/rkotler/workspace/llvm/lib/Target/Mips/MipsInstrInfo.td:1474:
/home/rkotler/workspace/llvm/lib/Target/Mips/Mips64InstrInfo.td:89:1:
error: Duplicate record in FastISel table!
def DSUB : ArithLogicR<"dsub", GPR64Opnd,...
2012 Nov 13
2
[LLVMdev] [PATCH] .gitignore: add rules for a clean worktree
...index 0000000..27c073c
--- /dev/null
+++ b/lib/Target/Mips/.gitignore
@@ -0,0 +1,12 @@
+MipsGenAsmMatcher.inc
+MipsGenAsmWriter.inc
+MipsGenCallingConv.inc
+MipsGenCodeEmitter.inc
+MipsGenDAGISel.inc
+MipsGenDisassemblerTables.inc
+MipsGenEDInfo.inc
+MipsGenInstrInfo.inc
+MipsGenMCCodeEmitter.inc
+MipsGenMCPseudoLowering.inc
+MipsGenRegisterInfo.inc
+MipsGenSubtargetInfo.inc
diff --git a/lib/Target/NVPTX/.gitignore b/lib/Target/NVPTX/.gitignore
new file mode 100644
index 0000000..74001d1
--- /dev/null
+++ b/lib/Target/NVPTX/.gitignore
@@ -0,0 +1,5 @@
+NVPTXGenAsmWriter.inc
+NVPTXGenDAGISel.inc
+NVPTXGenInstrInfo.in...