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Hi All. This is an RFC for a proposed target specific X86 optimization for reducing code size in the encoding of AVX-512 instructions when possible. When the AVX512F instruction set was introduced in X86 it included additional 32 registers of 512bit size each ZMM0 - ZMM31, as well as additional 16 XMM registers XMM16-XMM31 and 16 YMM registers YMM16-YMM31. In order to encode the new registers of

...to have TableGen generate the mapping table for you > instead of manually making a table yourself. TableGen has a feature that is > specifically designed to make mapping tables like this. For examples, grep > for InstrMapping in: > > lib/Target/Hexagon/Hexagon.td > lib/Target/Mips/MipsDSPInstrFormats.td > lib/Target/Mips/MipsInstrFormats.td > lib/Target/Mips/Mips32r6InstrFormats.td > lib/Target/PowerPC/PPC.td > lib/Target/AMDGPU/SIInstrInfo.td > lib/Target/AMDGPU/R600Instructions.td > lib/Target/SystemZ/SystemZInstrFormats.td > lib/Target/Lanai/LanaiInstrInfo.td > > I...

...it stage. It might be better to have TableGen generate the mapping table for you instead of manually making a table yourself. TableGen has a feature that is specifically designed to make mapping tables like this. For examples, grep for InstrMapping in: lib/Target/Hexagon/Hexagon.td lib/Target/Mips/MipsDSPInstrFormats.td lib/Target/Mips/MipsInstrFormats.td lib/Target/Mips/Mips32r6InstrFormats.td lib/Target/PowerPC/PPC.td lib/Target/AMDGPU/SIInstrInfo.td lib/Target/AMDGPU/R600Instructions.td lib/Target/SystemZ/SystemZInstrFormats.td lib/Target/Lanai/LanaiInstrInfo.td I've used this feature a few times in the...

...it stage. It might be better to have TableGen generate the mapping table for you instead of manually making a table yourself. TableGen has a feature that is specifically designed to make mapping tables like this. For examples, grep for InstrMapping in: lib/Target/Hexagon/Hexagon.td lib/Target/Mips/MipsDSPInstrFormats.td lib/Target/Mips/MipsInstrFormats.td lib/Target/Mips/Mips32r6InstrFormats.td lib/Target/PowerPC/PPC.td lib/Target/AMDGPU/SIInstrInfo.td lib/Target/AMDGPU/R600Instructions.td lib/Target/SystemZ/SystemZInstrFormats.td lib/Target/Lanai/LanaiInstrInfo.td I've used this feature a few times in the...