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Hello, I am trying to improve lib/Target/Mips/MipsDelaySlotFiller.cpp by substituting nops emitting with instructions reordering. I need a hazard recognizer, but I haven't found any. Do I have to create one, or looking bad and there is any? Thanks for any reply. -- Filip Kocina, student FIT Email: xkocin00 at stud.fit.vutbr.cz

...f there isn't anything which can be scheduled between the two instructions. > What would be the right way to specify a latency of 2 with 1 clk initiation > interval for instance If you need to insert NOP's between certain instructions, you should use a separate pass to do that. See MipsDelaySlotFiller.cpp for an example of such a pass. -Eli

Hi everyone I'm fairly new with LLVM and I've been searching around but couldn't find info on this subject. I started working on a target for a new cpu and I realizing my initial simple understanding of instruction itineraries may be completely off. I'm trying to model a CPU that has a latency of 2 cycles for multiplications fully pipelined (so it can start a new one after one

Hi Filip, > I am trying to improve lib/Target/Mips/MipsDelaySlotFiller.cpp by > substituting nops emitting with instructions reordering. I need > a hazard recognizer, but I haven't found any. Do I have to create > one, or looking bad and there is any? You have to create one! Take a look at PPCHazardRecognizers.cpp and SPUHazardRecognizers.cpp for exam...

...can be scheduled between the two instructions. > > > What would be the right way to specify a latency of 2 with 1 clk > initiation > > interval for instance > > If you need to insert NOP's between certain instructions, you should > use a separate pass to do that. See MipsDelaySlotFiller.cpp for an > example of such a pass. > > -Eli > -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20110816/09d1d543/attachment.html>

Hello. Hal, the problem I have is that it doesn't advance at the next available instruction - it always gets the same store. This might be because I did not specify in a file like [Target]Schedule.td the functional units, processor and instruction itineraries. Regarding the Stalls argument to my method [Target]DispatchGroupSBHazardRecognizer::getHazardType() I always get the