search for: mips64gprreg

...that are context sensitive. For instance, the 32 general purpose registers for both Mips32 and Mips64 have the same name, but each of the Mips32 registers are just a subregister in their Mips64 instance. def AT : MipsGPRReg< 1, "AT">, DwarfRegNum<[1]>; def AT_64 : Mips64GPRReg< 1, "AT", [AT]>; It gets more interesting with floating point where we have 3 different configurations, single precision, double precision aliased with single precision pair and straight double point precision. All of which share the same register name. /// Mips Single point p...

...e. > > For instance, the 32 general purpose registers for both Mips32 and Mips64 have the same name, but each of the Mips32 registers are just a subregister in their Mips64 instance. > > def AT : MipsGPRReg< 1, "AT">, DwarfRegNum<[1]>; > def AT_64 : Mips64GPRReg< 1, "AT", [AT]>; > > It gets more interesting with floating point where we have 3 different configurations, single precision, double precision aliased with single precision pair and straight double point precision. All of which share the same register name. > > ///...

...e. > > For instance, the 32 general purpose registers for both Mips32 and Mips64 have the same name, but each of the Mips32 registers are just a subregister in their Mips64 instance. > > def AT : MipsGPRReg< 1, "AT">, DwarfRegNum<[1]>; > def AT_64 : Mips64GPRReg< 1, "AT", [AT]>; > > It gets more interesting with floating point where we have 3 different configurations, single precision, double precision aliased with single precision pair and straight double point precision. All of which share the same register name. > > ///...