search for: mips32r6

...since they represent the generations of the MIPS ISA. If these extensions are available in Loongson chips based on MIPS32r1 and MIPS32r2 for example, it becomes difficult to describe with ISA_* classes without duplicating instruction definitions or setting up complicated subsets (like we had to for MIPS32r6 to deal with the instruction removals). I would recommend the ASE_* classes which are intended for application specific extensions. These are used for optional extensions to the MIPS ISA such as MSA or DSP, but are also used for vendor specific extensions to the MIPS ISA such as cnMIPS. The ASE_CN...

...te. I'm going to try a build with that patch reverted to confirm this and assuming I'm right I'll revert this merge. > clang+llvm-3.6.1-rc1-x86_64-linux-gnu-ubuntu-14.04.tar.xz (cross compiling to Mips) > * Still running. > * For the 'mipsel-img-linux-gnu -mips32r6 -mfpxx', 'mipsel-img-linux-gnu -mmicromips' test runs I have > several regressions that look like timeouts caused by a busy system. I'm re-running these at the > moment and they are passing so far. Just a quick update: The 'mipsel-img-linux-gnu -mips...

Hi, I have tagged the 3.6.1-rc1 so testing can begin. We can always use more testers, so if you are interested in helping, let me know. Instructions for validating an LLVM release can be found here: http://llvm.org/docs/ReleaseProcess.html Reminder: We are using 3.6.0 as our baseline for regression testing. Thanks, Tom

...ot exactly. We're not working on any completely new ABI's but we are >> fixing a compatibility flaw between the O32 ABI and a (currently) >> unsupported extension that allows the efficient use of FR=1 mode (FPU >> with 64-bit registers). This is going to be important since MIPS32r6/MIPS64r6 >> will not have direct support for FR=0 mode (FPU with 32-bit registers). At >> the moment, this extension is available in all the tools and is enabled with - >> mfp64. Unfortunately, it is not possible to inter-link O32 and O32+fp64 code >> since they require the...

But then I should write // CHECK: something // SSE: something // SSE3: something With this feature it can be write // {{[A-Z0-9]+}} : something From: James Y Knight [mailto:jyknight at google.com] Sent: Thursday, May 26, 2016 5:53 PM To: Ehsan Amiri <ehsanamiri at gmail.com> Cc: Elena Lepilkina <Elena.Lepilkina at synopsys.com>; llvm-dev <llvm-dev at lists.llvm.org> Subject:

Hi LLVM developers, GCC[1] is able to use Loongson ISA[2] for instruction selection: $ cat hello.c #include <stdio.h> int main(int argc, char *argv[]) { printf("Hello World\n"); return 0; } $ gcc -O0 -S hello.c $ cat hello.s .file 1 "hello.c" .section .mdebug.abi64 .previous .nan legacy .gnu_attribute 4, 1 .abicalls

On Thu, May 26, 2016 at 10:35 AM, Ehsan Amiri via llvm-dev < llvm-dev at lists.llvm.org> wrote: > 7. Wildcard for prefixes - If some statements should be checked > regardless prefix, it should be used //{{*}}, //{{*}}-NEXT, //{{*}}-SAME > and etc. > >> 8. Prefix with regular expressions - If statement should be >> checked if prefix matches some regular

...d to make r227089 apply cleanly. * Testcase from r221686 - [mips] Add preliminary support for the MIPS II target. o Only the testcase minus the MIPS-II cases should be merged. o Required to make r227089 apply cleanly. * r226171 - [mips] Fix a typo in the compare patterns for MIPS32r6/MIPS64r6. o Fixes bad code generation in the test-suite for certain option combinations. * r225529 - [mips] Add support for accessing $gp as a named register. o Fixes bad code generation in LLVMLinux * r224425 and r225521 - [mips] Set GCC-compatible MIPS asssembler options b...

The term "target" is somewhat overloaded. When llvm-config tells you it was built with the X86 target, that actually includes a variety of closely related architectures, such as x86_64, i386, and so on. Within the x86_64 architecture, there are many individual processor implementations that LLVM understands, such as Skylake, Bulldozer, and many many more. What *clang* means by

...ves introduce references on particular ABI's and not on others. I think this information would be best delivered via the LLVM-IR but adding the ABI in LLVM-IR files has been strongly opposed in previous discussions. Also, IRObjectFile may need the CPU due to some changes to relocation rules for MIPS32R6 that prevent elimination of relocations that can be evaluated locally which would lead to the same issue. The other callers of createMCAsmInfo() either already have the ABI by one means or another, or would be able to figure it out if we extend ObjectFile to detect the ABI from the object*. Some o...

I am working on an LLVM backend for the AVR architecture, and am having troubles working with the codegen layer, trying to get around the quirks of the binary encodings of the AVR ISR. There are several different families of AVR microcontrollers, each with a minimum 'core' instruction set. Each family builds upon (or removes) the core ISR with more instructions or different encodings. My

On Wed, Jun 18, 2014 at 2:03 AM, Matheus Almeida <Matheus.Almeida at imgtec.com> wrote: >> Why Imagination Technologies do not offer the latest MIPS ABI document download link just like the ISA docs? > It's something we're considering to do and the documents should be available at some point in the [hopefully] not too distant future. > >> then why GCC disagree with

...abi right now. > > Not exactly. We're not working on any completely new ABI's but we are fixing a compatibility flaw between the O32 ABI and a (currently) unsupported extension that allows the efficient use of FR=1 mode (FPU with 64-bit registers). This is going to be important since MIPS32r6/MIPS64r6 will not have direct support for FR=0 mode (FPU with 32-bit registers). At the moment, this extension is available in all the tools and is enabled with -mfp64. Unfortunately, it is not possible to inter-link O32 and O32+fp64 code since they require the FPU to be in different modes. To fix...

On 24 June 2016 at 06:02, Daniel Sanders <Daniel.Sanders at imgtec.com> wrote: > Hi, > > Having recently enabled IAS by default for the MIPS O32 ABI, I'm now trying to do the same thing for the MIPS N64 ABI. Unfortunately, it is not currently possible to enable IAS by default for the N64 ABI without also enabling it for the N32 ABI because this information is not reflected in

Hi everyone, There was idea to add new directives to FileCheck: 1. Directive to use some patterns as named template with or without parameters. 2. CHECK-INCLUDE - Directive to include other file with checks to another. 3. Expressions repeat for CHECK - If statement should be checked several times repeat modifiers {n}, {n,m} , {,n}, {n,}, *, + can be used. 4. Repeat in

Hello, I am developing GlobalISel for MIPS. I have a few questions and observations about defining legality of generic instruction and also possible combining of instructions and artifacts in pre/post legalizer combiner or elsewhere (e.g. in some sort of instruction-select patterns). I look at legality as "If generic instruction can be selected into machine instruction, it is legal".

...epts the following MIPS CPU names. This list can be found in the "clang/lib/Basic/Targets/Mips.cpp". mips1 and mips5 accepted by Clang, but unsupported by code generator. I'm going to remove them from this list. mips1, mips2, mips3, mips4, mips5, mips32, mips32r2, mips32r3, mips32r5, mips32r6, mips64, mips64r2, mips64r3, mips64r5, mips64r6, octeon, octeon+, p5600 R3000 is a CPU implements mips1 instruction set architecture. Unfortunately you cannot generate a code for this CPU using Clang. -- Simon Atanasyan Als GmbH eingetragen im Handelsregister Bad Homburg v.d.H. HRB 9816, USt.ID-N...

Hi, Having recently enabled IAS by default for the MIPS O32 ABI, I'm now trying to do the same thing for the MIPS N64 ABI. Unfortunately, it is not currently possible to enable IAS by default for the N64 ABI without also enabling it for the N32 ABI because this information is not reflected in the triple and that's the only information MipsMCAsmInfo has. This would be fine if it N32 was

...do you believe '-triple mipsel-linux-gnu' means? You're probably thinking something like "mips32r2 little endian, obviously" but this is not actually correct all the time. The true answer is 'whatever I (the person who built the toolchain) want it to mean'. It could be mips32r6, it could be mips4, it could even be big-endian mips64r5 with nan2008 and msa. It could even be octeon or p5600. In GCC toolchains, distributors routinely use configure-time options to define the triple they wish to use. Nothing is stopping anyone using the same string for completely different mean...

I think we need to take a step further back and re-enter from the right starting point. The thing that's bothering me about the push back so far is that it's trying to discuss and understand the consequences of resolving the core problem while seemingly ignoring the core problem itself. The reason I've been steering everything back to GNU Triple's being ambiguous and inconsistent