search for: mips32

I'm working on the mips16. Mips16 is a mode of the Mips32 (or Mips64) processor. For the most part, it is a compressed form of the MIPS32 instruction set, though not all instructions are supported. Most of the same opcodes and formats are present though sometimes with some restriction. (The micro mips architecture is a true 16 bit compressed form of...

...r Micro Mips is not present, then I want the subfeature "standard encoding". If I can't do this, then it requires me to write a more complex expression for the "standard encoding" expresions. For mips , mips16 and micro mips are considered to be processor extenasions to mips32 and mips64. So usually you would build a mips32 or mips64 compiler and then add -mips16 to the command line. Right now, there are no implementations of micro mips or mips16 with mips 64, though architecturally it is defined. So the options would be: -mips16 -mips32 -micromips -mips64 With th...

I'm working on mips16 hard float which at a first approximation is just soft float but calls different library routines. Those different library routines are just an implementation (in mips32 mode) of soft float using mips32 hardware instructions. This part is already done. (mips16 mode has no floating point instructions). The next level of this that I am working on now is the ability to call mips32 mode functions from mips16. This is needed for example to call the math library (si...

What I am thinking of now is to just register the MIPS116 and MIPS32 DAGToDAGISel passes and then within run on machine function, I can just return if the current mode indicates that mips16 is needed for example, so the run on machine function for Mips32 would return immediately. On 03/27/2013 10:05 AM, Reed Kotler wrote: > I guess another way to do this is to...

...> On Fri, Jan 4, 2013 at 4:08 PM, reed kotler <rkotler at mips.com> wrote: >> I'm working on mips16 hard float which at a first approximation is just soft >> float but calls different library routines. Those different library routines >> are just an implementation (in mips32 mode) of soft float using mips32 >> hardware instructions. This part is already done. (mips16 mode has no >> floating point instructions). >> >> The next level of this that I am working on now is the ability to call >> mips32 mode functions from mips16. This is needed...

On Jan 24, 2012, at 1:46 AM, Reed Kotler wrote: > Mips16 is a mode of the Mips32 (or Mips64) processor. For the most part, > it is a compressed form of the MIPS32 instruction set, though not all > instructions are supported. Most of the same opcodes and formats are > present though sometimes with some restriction. (The micro mips > architecture is a true 16 bit...

...t;rkotler at mips.com> wrote: >>> >>> I'm working on mips16 hard float which at a first approximation is just >>> soft >>> float but calls different library routines. Those different library >>> routines >>> are just an implementation (in mips32 mode) of soft float using mips32 >>> hardware instructions. This part is already done. (mips16 mode has no >>> floating point instructions). >>> >>> The next level of this that I am working on now is the ability to call >>> mips32 mode functions from mip...

...er at mips.com> wrote: >>>> I'm working on mips16 hard float which at a first approximation is just >>>> soft >>>> float but calls different library routines. Those different library >>>> routines >>>> are just an implementation (in mips32 mode) of soft float using mips32 >>>> hardware instructions. This part is already done. (mips16 mode has no >>>> floating point instructions). >>>> >>>> The next level of this that I am working on now is the ability to call >>>> mips32 mod...

...eferenced under certain optimizations. This is part of the gcc mips16 hack for floating point. For example, a function like floor from the math library will be called with an external reference to function floor. At that time, the compiler does not know whether floor was compiled as mips16 or mips32. It generates the call to floor as if it is a mips16 compiled function. It also generates a stub that the linker can use if during link time it is discovered that "floor" is a mips32 function. The stubs, which are mips32 code, will move the first argument register into a floating poi...

I'm implementing this ability to switch between mips16 and mips32 on a per function basis. One issue that I've run into is regarding the DAGToDAGIsel pass. We have a different subclass for mips16 and non mips16 ( conceivably later there could be a separate one for micromips). I need to run a different pass depending on whether it's mips16 or mips32....

Micro mips is really 100% .s compatible with mips32. There are no register field size constraints and such. It's a strict superset of mips32. For the gcc port, the assembler is basically the only thing we changed. The gcc port was just adding the ".micromips" directive to the .s file and maybe some tiny driver work. That is the q...

The problem is that everything about the mips32 and micro mips 16 instruction is the same, aside from the encoding in to binary. Seems like maybe we need to extend the notion of an instruction so that it can have alternate encodings depending on subtarget. On 09/05/2012 08:28 PM, Jim Grosbach wrote: > The instructions are defined by their...

...ro mips was similar to Thumb2, in that the smaller encodings have constraints on which registers can be read/written, because of the narrowing of the register fields in the encoding. If that's the case, then it definitely makes sense to model the micro mips instruction set as distinct from the mips32 instruction set, in basically the same way that Thumb2 is done. The reason for this is this: in micro mips mode, you're going to need to split each opcode with a 16-bit variant (say, ADD) into two versions: the 16-bit version with constrained input/output registers, and the 32-bit version with...

...;> >>>>> I'm working on mips16 hard float which at a first approximation is just >>>>> soft >>>>> float but calls different library routines. Those different library >>>>> routines >>>>> are just an implementation (in mips32 mode) of soft float using mips32 >>>>> hardware instructions. This part is already done. (mips16 mode has no >>>>> floating point instructions). >>>>> >>>>> The next level of this that I am working on now is the ability to call >>&gt...

On Fri, Jan 4, 2013 at 4:08 PM, reed kotler <rkotler at mips.com> wrote: > I'm working on mips16 hard float which at a first approximation is just soft > float but calls different library routines. Those different library routines > are just an implementation (in mips32 mode) of soft float using mips32 > hardware instructions. This part is already done. (mips16 mode has no > floating point instructions). > > The next level of this that I am working on now is the ability to call > mips32 mode functions from mips16. This is needed for example to call...

Yes, you could have mips16 and fastcc. Mips16 just means that processor mode to execute that function is "mips16". So in a mips16 designated function, I will just emit mips16 instructions and in a "nomips16" function, just emit normal mips32 instructions. I tend to call this "mips32" normal mode, "standard encoding" because in reality the processor is mips32 for both "mips16" and "nomips16". Nomips16 means normal "mips32" mode at this time. (We are mimicking the way gcc handles this...

Hello, I've built LLVM natively on a fpu-less (soft-float) mips32 target, and built mesa to use it. However llvm apparently cannot determine what machine it's running on and builds code for a generic mips target with fpu. Is there a way to have llc/llvm always use "-march=mipsle -mcpu=mips32 -mattr=+soft-float" as a default command line, something...

...ake-check at least passes in this case. So in principle turn on the dual mode now and debug whatever misc is left. For this I insert another pass before the mips16 and non mips16 passes. On 03/27/2013 10:19 AM, Reed Kotler wrote: > What I am thinking of now is to just register the MIPS116 and MIPS32 > DAGToDAGISel passes and then within run on machine function, I can just > return if the current mode indicates that mips16 is needed for example, > so the run on machine function for Mips32 would return immediately. > > On 03/27/2013 10:05 AM, Reed Kotler wrote: >> I guess an...

I guess another way to do this is to just register both passes for mips16 and mips32 and have them return immediately if it is not their turn to run. On 03/27/2013 08:58 AM, Reed Kotler wrote: > I'm implementing this ability to switch between mips16 and mips32 on a > per function basis. > > One issue that I've run into is regarding the DAGToDAGIsel pass. >...

So the switching between mips16 and mips32 on a per function basis seems to basically be working except that asm printer has some kind of issue here. I'm debugging that now. I get this: lc: /home/rkotler/workspace/llvmpb6/include/llvm/MC/MCStreamer.h:224: void llvm::MCStreamer::SwitchSection(const llvm::MCSection*): Assertion `Sect...