Displaying 20 results from an estimated 255 matches for "mips16e".
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2013 Jan 11
2
[LLVMdev] adding IR attributes to llvm
Yes, you could have mips16 and fastcc.
Mips16 just means that processor mode to execute that function is "mips16".
So in a mips16 designated function, I will just emit mips16 instructions 
and in a "nomips16"
function, just emit normal mips32 instructions.
I tend to call this "mips32" normal mode, "standard encoding" because in 
reality the processor is
2013 Feb 05
2
[LLVMdev] register scavenging
I ran into a case in Mips16 where I need two registers.
The problem arises from the fact that SP is not a mips16 register.
You can implicitly use it in load/store and, move it to/from a mips16 
register and add small immediate values to it but that's it.
It's not in general a problem for me because there are a bunch of mips32 
registers that are hard to use in mips16 so at this time, I
2012 May 17
2
[LLVMdev] subtarget features
Is it possible to assign the value of subtarget features using more 
complex expressions with code as opposed to using the mechanism that 
tablegen affords.
For example, if Mips16 or Micro Mips is not present, then I want the 
subfeature "standard encoding".
If I can't do this, then it requires me to write a more complex 
expression for the "standard encoding" expresions.
2013 Jan 11
0
[LLVMdev] adding IR attributes to llvm
I think that Bill Wendlings new attribute implementation would allow me 
to do this but it is not ready yet.
Maybe it's okay to just add them to the list of function attributes as I 
suggested.
But in the end, someone has to approve the checkin.
On 01/11/2013 07:35 AM, Reed Kotler wrote:
> Yes, you could have mips16 and fastcc.
>
> Mips16 just means that processor mode to execute
2013 Mar 27
2
[LLVMdev] LLVM pass question
What I am thinking of now is to just register the MIPS116 and MIPS32 
DAGToDAGISel passes and then within run on machine function, I can just
return if the current mode indicates that mips16 is needed for example, 
so the run on machine function for Mips32 would return immediately.
On 03/27/2013 10:05 AM, Reed Kotler wrote:
> I guess another way to do this is to just register both passes for
2013 Feb 06
2
[LLVMdev] register scavenging
So what I realized is that you can't use the simple scavenger trick 
where you create the virtual register and use the more advanced features.
This is because you can't call forward() in any form if there are 
virtual registers being used by any of the instructions in the basic 
block. This will cause forward to fail.
Maybe this is a bug in forward()
On 02/05/2013 02:51 PM, Reed Kotler
2012 Jan 20
4
[LLVMdev] various mips16 and micro mips issues
We are starting to look at the mips16 and micro mips ports.
There are various design issues that people may have some good input on.
Especially in how to structure the TD files and other optimizer issues.
Mips16 is sort of like thumb and Micro Mips like thumb2 as far as I 
understand.
Mips16 or Micro Mips can live inside of either MIPS32 or MIPS64.
In gcc, it's possible using attributes to
2013 Mar 27
0
[LLVMdev] LLVM pass question
This seems to work okay.
I register both the Mips16 and non Mips16 passes of the instruction 
selector and then those return false if they are not supposed to be running.
Make-check at least passes in this case.
So in principle turn on the dual mode now and debug whatever misc is left.
For this I insert another pass before the mips16 and non mips16 passes.
On 03/27/2013 10:19 AM, Reed Kotler
2013 Feb 05
0
[LLVMdev] register scavenging
Does not seem that anyone is using the more advanced features of 
RegScavenger
On 02/05/2013 01:09 PM, reed kotler wrote:
> I ran into a case in Mips16 where I need two registers.
>
> The problem arises from the fact that SP is not a mips16 register.
> You can implicitly use it in load/store and, move it to/from a mips16
> register and add small immediate values to it but
2012 Jan 24
3
[LLVMdev] mips16
I'm working on the mips16.
Mips16 is a mode of the Mips32 (or Mips64) processor. For the most part, 
it is a compressed form of the MIPS32 instruction set, though not all 
instructions are supported. Most of the same opcodes and formats are 
present though sometimes with some restriction.  (The micro mips 
architecture is a true 16 bit compressed form of MIps32 though also with 
some
2013 Mar 27
1
[LLVMdev] LLVM pass question
So the switching between mips16 and mips32 on a per function basis seems 
to basically be working except that asm printer has some kind of
issue here.
I'm debugging that now.
I get this:
lc: /home/rkotler/workspace/llvmpb6/include/llvm/MC/MCStreamer.h:224: 
void llvm::MCStreamer::SwitchSection(const llvm::MCSection*): Assertion 
`Section && "Cannot switch to a null
2012 Jan 20
0
[LLVMdev] various mips16 and micro mips issues
On Fri, Jan 20, 2012 at 1:59 PM, reed kotler <rkotler at mips.com> wrote:
> We are starting to look at the mips16 and micro mips ports.
>
> There are various design issues that people may have some good input on.
> Especially in how to structure the TD files and other optimizer issues.
>
> Mips16 is sort of like thumb and Micro Mips like thumb2 as far as I
> understand.
2013 Feb 06
0
[LLVMdev] register scavenging
No. forward() is working correctly. All virtual register references must be resolved before calling it.
-Jim
On Feb 5, 2013, at 4:05 PM, Reed Kotler <rkotler at mips.com> wrote:
> So what I realized is that you can't use the simple scavenger trick where you create the virtual register and use the more advanced features.
> 
> This is because you can't call forward() in any
2013 Jan 08
2
[LLVMdev] mips16 hard float puzzle
On 01/04/2013 07:45 PM, Eli Friedman wrote:
> On Fri, Jan 4, 2013 at 6:28 PM, reed kotler <rkotler at mips.com> wrote:
>> On 01/04/2013 06:08 PM, Eli Friedman wrote:
>>> On Fri, Jan 4, 2013 at 4:08 PM, reed kotler <rkotler at mips.com> wrote:
>>>> I'm working on mips16 hard float which at a first approximation is just
>>>> soft
2013 Jan 08
0
[LLVMdev] mips16 hard float puzzle
On Mon, Jan 7, 2013 at 4:16 PM, reed kotler <rkotler at mips.com> wrote:
> On 01/04/2013 07:45 PM, Eli Friedman wrote:
>>
>> On Fri, Jan 4, 2013 at 6:28 PM, reed kotler <rkotler at mips.com> wrote:
>>>
>>> On 01/04/2013 06:08 PM, Eli Friedman wrote:
>>>>
>>>> On Fri, Jan 4, 2013 at 4:08 PM, reed kotler <rkotler at mips.com>
2013 Jan 05
2
[LLVMdev] mips16 hard float puzzle
I'm working on mips16 hard float which at a first approximation is just 
soft float but calls different library routines. Those different library 
routines are just an implementation (in mips32 mode) of soft float using 
mips32 hardware instructions. This part is already done. (mips16 mode 
has no floating point instructions).
The next level of this that I am working on now is the ability to
2013 Jan 05
4
[LLVMdev] mips16 hard float puzzle
On 01/04/2013 06:08 PM, Eli Friedman wrote:
> On Fri, Jan 4, 2013 at 4:08 PM, reed kotler <rkotler at mips.com> wrote:
>> I'm working on mips16 hard float which at a first approximation is just soft
>> float but calls different library routines. Those different library routines
>> are just an implementation (in mips32 mode) of soft float using mips32
>>
2013 Mar 27
2
[LLVMdev] LLVM pass question
I'm implementing this ability to switch between mips16 and mips32 on a 
per function basis.
One issue that I've run into is regarding the DAGToDAGIsel pass.
We have a different subclass for mips16 and non mips16 ( conceivably 
later there could be a separate one for micromips).
I need to run a different pass depending on whether it's mips16 or mips32.
My initial plan was to create
2013 Jan 11
2
[LLVMdev] adding IR attributes to llvm
For target dependent function level attributes, do I need to actually 
add them to the enumeration in attributes.h?
I have for example, mips16 and nomips16 as attributes.
Or is this supposed to be done with cc <n>
2012 May 14
4
[LLVMdev] getMinimalPhysRegClass
On 05/14/2012 02:17 PM, Jakob Stoklund Olesen wrote:
> On May 14, 2012, at 1:02 PM, reed kotler wrote:
>
>> Does anyone understand the purpose of :
>>
>> TargetRegisterInfo::getMinimalPhysRegClass ???
> Barely.
>
>> Why is there the presumption to use the minimal subclass?
> The function can be traced back to a time when men were men and registers belonged to