search for: mip32

Displaying 12 results from an estimated 12 matches for "mip32".

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2013 Feb 05
2
[LLVMdev] register scavenging
...mips32 only register. What I need is somewhere to move SP so that I can use it in another instruction. mov unused mips32 register, temp mips16 register; if temp is being used mov temp mips16 register, SP add.....temp mips16 register.... ; temp is no longer needed mov temp mips16 register, unused mip32 register ; if temp was being used This is my main problem. ---------------------------------------------------------------------- There is another issue from the point of view of optimization and that is that if I'm going to be doing this a lot, then this copy of SP is a CSE and should be tr...
2013 Sep 26
1
[LLVMdev] adding multiple flavors to test suite
...d by this. Basically an ABI test for this. This program is a multi source because the two modules can't know if the other is compiled with mips16 or mips32. For this one test, there are 64 different combinations to test. This is from [little endian , big endian] [file 1 compiled as mips16|mip32] [file2 compiled as mips16|mips32] [compiled as pic, static] [linked as static, non static] [compiled as one command or separate clang commands] ... [soft float, hard float] The tests run very quickly. They are really ABI tests. There are some other tests beyond this basic ABI test that need to a...
2013 Feb 06
2
[LLVMdev] register scavenging
...that I can use it in another >> instruction. >> >> mov unused mips32 register, temp mips16 register; if temp is being used >> mov temp mips16 register, SP >> add.....temp mips16 register.... >> ; temp is no longer needed >> mov temp mips16 register, unused mip32 register ; if temp was being used >> >> This is my main problem. >> >> ---------------------------------------------------------------------- >> There is another issue from the point of view of optimization and that >> is that if I'm going to be >> doin...
2013 Feb 05
0
[LLVMdev] register scavenging
...d is somewhere to move SP so that I can use it in another > instruction. > > mov unused mips32 register, temp mips16 register; if temp is being used > mov temp mips16 register, SP > add.....temp mips16 register.... > ; temp is no longer needed > mov temp mips16 register, unused mip32 register ; if temp was being used > > This is my main problem. > > ---------------------------------------------------------------------- > There is another issue from the point of view of optimization and that > is that if I'm going to be > doing this a lot, then this copy...
2013 Feb 06
0
[LLVMdev] register scavenging
...>>> instruction. >>> >>> mov unused mips32 register, temp mips16 register; if temp is being used >>> mov temp mips16 register, SP >>> add.....temp mips16 register.... >>> ; temp is no longer needed >>> mov temp mips16 register, unused mip32 register ; if temp was being used >>> >>> This is my main problem. >>> >>> ---------------------------------------------------------------------- >>> There is another issue from the point of view of optimization and that >>> is that if I'm...
2013 Apr 25
1
[LLVMdev] issues with InlineAsm class and #APP/#NOAPP
...oating point registers that are used to return values, to where soft float would have mapped them to. In this case, it means that F0 must be copied to integer return register R2. So this helper stub will work whether in reality fpff is compiled as mips16 or mips32. There are similar issues for mip32 code calling mips16 code. Return types that can be passed in registers include float, double, _Complex float and _Complex double. Parameter signatures of the form below need to be remapped: float double float, double float, float double, double double, float .section .mips16.call.fp.fpff,&quot...
2012 Aug 08
0
[LLVMdev] another mips16 puzzle
i'm trying to formulate the optimal way to do comparison testing for mips 16. on mips32 there are no condition codes. you can test a<b and place the result in a register in mip32. on mips16 you can do the same, however, the register is always T8==24. T8 is not directly accessible by most mips16 instructions, but can be directly moved to a generally accessible mips16 register, and can also used in tests for a conditional branch. later you can conditionally branch based...
2012 Nov 14
0
[LLVMdev] mips16 patches in the works
...ng on so that nobody else duplicates it: 1) Fix exception handling for Mips 16. Patch already pushed for review. 2) Finish up handling of large frames. 90% of code done and being tested. One more patch is needed. 3) Hard float. (mips16 has no floating point instructions so you need to switch to mip32 mode to do this). Design is mostly done. Estimate of 3-4 weeks for implementation and testing of non optimized version. Will not start on coding of this till test-suite at near to 100% passing for all of mips 16 using soft float. 4) Constant islands. Preliminary design in progress.
2013 Apr 24
0
[LLVMdev] issues with InlineAsm class and #APP/#NOAPP
> We also wanted the stubs to be real functions to llvm. That allows them to > participate properly > in optimization of various levels (including LTO). They can even be inlined. > There are other > planned optimizations that would not work if they were not legitimate > functions. I am not saying that the functions should not exist in the IL, just that they should not be inline
2013 Apr 24
3
[LLVMdev] issues with InlineAsm class and #APP/#NOAPP
On 04/24/2013 03:47 PM, Rafael EspĂ­ndola wrote: > On 24 April 2013 18:30, reed kotler <rkotler at mips.com> wrote: >> There are a lot of issues. >> >> For one, the function I'm compiling is a mips16 function but the stubs being >> created are mips32 functions. >> > This looks similar to thumb x 32 bit arm. Wouldn't a similar solution > work for
2013 Apr 01
0
[LLVMdev] proposed change to class BasicTTI and dual mode mips16/32 working
On 04/01/2013 12:31 PM, Chandler Carruth wrote: > On Thu, Mar 28, 2013 at 12:22 PM, Nadav Rotem <nrotem at apple.com > <mailto:nrotem at apple.com>> wrote: > > IMHO the right way to handle target function attributes is to > re-initialize the target machine and TTI for every function (if > the attributes changed). Do you have another solution in mind ?
2013 Apr 01
3
[LLVMdev] proposed change to class BasicTTI and dual mode mips16/32 working
On Thu, Mar 28, 2013 at 12:22 PM, Nadav Rotem <nrotem at apple.com> wrote: > IMHO the right way to handle target function attributes is to > re-initialize the target machine and TTI for every function (if the > attributes changed). Do you have another solution in mind ? I don't really understand this. TargetMachine and TTI may be quite expensive to initialize. Doing so for